Internet Data Sheet
HYB25DC128[800/160]C[E/F]
128-Mbit Double-Data-Rate SDRAM
4.3
IDD Current Measurement Conditions
Legend: A = Activate, R = Read, RA = Read with Autoprecharge, P = Precharge, N = NOP or DESELECT
I
DD1: Operating Current: One Bank Operation
1. General test condition
a) Only one bank is accessed with tRC,MIN
.
b) Burst Mode, Address and Control inputs are changing once per NOP and DESELECT cycle.
c) 50% of data changing at every transfer
d) IOUT = 0 mA.
2. Timing patterns
a) DDR266A (133 MHz, CL = 2): tCK = 7.5 ns, BL = 4, tRCD = 3 × tCK, tRC = 9 × tCK, tRAS = 5 × tCK
Setup: A0 N N R0 N P0 N N N Read: A0 N N R0 N P0 N NN - repeat the same timing with random address changing
b) DDR333B (166 MHz, CL = 2.5): tCK = 6 ns, BL = 4, = 3 × tCK, tRC = 10 × tCK, tRAS = 7 × tCK
Setup: A0 N N R0 N N N P0 N N Read: A0 N N R0 N N N P0 N N - repeat the same timing with random address changing
c) DDR400B (200 MHz, CL = 3): tCK = 5 ns, BL = 4, tRCD = 3 × tCK, tRC = 11 × tCK, tRAS = 8 × tCK
Setup:A0 N N R0 N N N N P0 N N Read: A0 N N R0 N N N N P0 N N -repeat the same timing with random address
changing
I
DD7: Operating Current: Four Bank Operation
1. General test condition
a) Four banks are being interleaved with tRCMIN
.
b) Burst Mode, Address and Control inputs on NOP edge are not changing.
c) 50% of data changing at every transfer
d) IOUT = 0 mA.
2. Timing patterns
a) DDR266A (133 MHz, CL = 2): tCK = 7.5 ns, BL = 4, tRRD = 2 × tCK, tRCD = 3 × tCK, tRAS = 5 × tCK
Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 Read: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 - repeat the same timing with
random address changing
b) DDR333B (166 MHz, CL = 2.5): tCK = 6 ns, BL = 4, tRRD = 2 × tCK, tRCD = 3 × tCK, tRAS = 5 × tCK
Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 Read: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 - repeat the same timing with
random address changing
c) DDR400B (200 MHz, CL = 3): tCK = 5 ns, BL = 4, tRRD = 2 × tCK, tRCD = 3 *× tCK, tRAS = 8 × tCK
Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N Read: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N - repeat the same timing
with random address
Rev. 1.1, 2007-01
26
03062006-JXUK-E7R1
QIMONDA [ QIMONDA AG ]
