Internet Data Sheet
HYB25DC128[800/160]C[E/F]
128-Mbit Double-Data-Rate SDRAM
TABLE 21
DD Specification
I
Symbol
–5
–6
Unit
Note1) / Test Condition
DDR400B
DDR333B
IDD0
IDD1
90
75
75
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
×8 2)3)
×16 3)
×8 3)
×16 3)
3)
90
100
110
5
85
95
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
5
3)
3)
3)
3)
36
30
28
24
18
15
45
38
54
45
×16 3)
×8 3)
×16 3)
×8 3)
IDD4R
IDD4W
100
120
105
130
190
3.0
—
85
100
90
110
160
3.0
1.1
215
215
×16 3)
3)
IDD5
IDD6
4)
Low power 5)
×8 3)
×16 3)
IDD7
250
250
1) Test conditions: VDD = 2.7 V, TA = 10 °C
2) DD specifications are tested after the device is properly initialized and measured at 133 MHz for DDR266, 166 MHz for DDR333, and 200
MHz for DDR400.
I
3) Input slew rate = 1 V/ns.
4) Enables on-chip refresh and address counters.
5) Low power available on request
Rev. 1.1, 2007-01
25
03062006-JXUK-E7R1
QIMONDA [ QIMONDA AG ]
