欢迎访问ic37.com |
会员登录 免费注册
发布采购

HYB25DC512800CE-6 参数 Datasheet PDF下载

HYB25DC512800CE-6图片预览
型号: HYB25DC512800CE-6
PDF下载: 下载PDF文件 查看货源
内容描述: 512 - Mbit的双数据速率SDRAM [512-Mbit Double-Data-Rate SDRAM]
分类和应用: 存储内存集成电路光电二极管动态存储器双倍数据速率
文件页数/大小: 35 页 / 1891 K
品牌: QIMONDA [ QIMONDA AG ]
 浏览型号HYB25DC512800CE-6的Datasheet PDF文件第12页浏览型号HYB25DC512800CE-6的Datasheet PDF文件第13页浏览型号HYB25DC512800CE-6的Datasheet PDF文件第14页浏览型号HYB25DC512800CE-6的Datasheet PDF文件第15页浏览型号HYB25DC512800CE-6的Datasheet PDF文件第17页浏览型号HYB25DC512800CE-6的Datasheet PDF文件第18页浏览型号HYB25DC512800CE-6的Datasheet PDF文件第19页浏览型号HYB25DC512800CE-6的Datasheet PDF文件第20页  
Internet Data Sheet  
HYB25DC512[800/160]C[E/F]  
512-Mbit Double-Data-Rate SDRAM  
TABLE 11  
Truth Table 2: Clock Enable (CKE)  
Current State CKE n-1  
CKEn  
Command n  
Action n  
Note  
Previous  
Cycle  
Current  
Cycle  
1)  
2)  
Self Refresh  
Self Refresh  
Power Down  
Power Down  
All Banks Idle  
All Banks Idle  
Bank(s) Active  
L
L
X
Maintain Self-Refresh  
Exit Self-Refresh  
L
H
L
Deselect or NOP  
X
L
Maintain Power-Down  
Exit Power-Down  
L
H
L
Deselect or NOP  
Deselect or NOP  
AUTO REFRESH  
Deselect or NOP  
See Table 12  
H
H
H
H
Precharge Power-Down Entry  
Self Refresh Entry  
Active Power-Down Entry  
L
L
H
1)  
VREF must be maintained during Self Refresh operation  
2) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A minimum of 200  
clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.  
1. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.  
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.  
3. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.  
4. All states and sequences not shown are illegal or reserved.  
TABLE 12  
Truth Table 3: Current State Bank n - Command to Bank n (same bank)  
Current State CS  
RAS CAS WE Command  
Action  
Note  
1)2)3)4)5)6)  
Any  
H
L
L
L
L
X
H
L
L
L
X
H
H
L
X
H
H
H
L
Deselect  
NOP. Continue previous operation.  
1) to 6)  
1) to 6)  
1) to 7)  
1) to 7)  
No Operation  
Active  
NOP. Continue previous operation.  
Idle  
Select and activate row  
AUTO REFRESH  
L
MODE REGISTER  
SET  
1) to 6), 8)  
1) to 6), 8)  
1) to 6), 9)  
1) to 6), 8)  
1) to 6), 9)  
1) to 6), 10)  
Row Active  
L
L
L
L
L
L
H
H
L
L
H
L
Read  
Select column and start Read burst  
Select column and start Write burst  
Deactivate row in bank(s)  
L
Write  
H
L
L
Precharge  
Read  
Read (Auto  
Precharge  
Disabled)  
H
L
H
L
Select column and start new Read burst  
Truncate Read burst, start Precharge  
BURST TERMINATE  
H
H
Precharge  
H
L
BURST  
TERMINATE  
1) to 6), 8), 11)  
1) to 6), 8)  
Write (Auto  
Precharge  
Disabled)  
L
L
L
H
H
L
L
L
H
H
L
Read  
Select column and start Read burst  
Select column and start Write burst  
Truncate Write burst, start Precharge  
Write  
1) to 6), 9), 11)  
L
Precharge  
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 11 and after tXSNR/tXSRD has been met (if the previous state  
was self refresh).  
Rev. 1.3, 2006-12  
16  
03292006-W2FE-ELDX