欢迎访问ic37.com |
会员登录 免费注册
发布采购

HYB25DC512800CE-6 参数 Datasheet PDF下载

HYB25DC512800CE-6图片预览
型号: HYB25DC512800CE-6
PDF下载: 下载PDF文件 查看货源
内容描述: 512 - Mbit的双数据速率SDRAM [512-Mbit Double-Data-Rate SDRAM]
分类和应用: 存储内存集成电路光电二极管动态存储器双倍数据速率
文件页数/大小: 35 页 / 1891 K
品牌: QIMONDA [ QIMONDA AG ]
 浏览型号HYB25DC512800CE-6的Datasheet PDF文件第8页浏览型号HYB25DC512800CE-6的Datasheet PDF文件第9页浏览型号HYB25DC512800CE-6的Datasheet PDF文件第10页浏览型号HYB25DC512800CE-6的Datasheet PDF文件第11页浏览型号HYB25DC512800CE-6的Datasheet PDF文件第13页浏览型号HYB25DC512800CE-6的Datasheet PDF文件第14页浏览型号HYB25DC512800CE-6的Datasheet PDF文件第15页浏览型号HYB25DC512800CE-6的Datasheet PDF文件第16页  
                                                                        
                                                                                    
                                                                                              
                                  
                                   
                                    
                                    
                                     
                                      
                                      
                                       
                                        
                                          
                                           
                                            
             
              
                
                
                 
                  
                                                                                                                           
                                                                                                                            
                                                                                                                              
                                                                                                                               
                                                                                                                                
                                                                                                                                 
                                                                                                                                 
Internet Data Sheet  
HYB25DC512[800/160]C[E/F]  
512-Mbit Double-Data-Rate SDRAM  
%
            
$
             
ꢅꢀ  
%
                  
$
                   
ꢁꢀ  
ꢁꢀ  
Uꢀ  
$
                        
                         
ꢆꢀ  
$
                              
                               
ꢅꢀ  
$
                                   
                                     
ꢁꢀ  
UD LQ  
Zꢀ  
$
                                          
ꢉꢀ  
$
                                                
ꢇꢀ  
$
                                                      
ꢊꢀ  
$
                                                           
ꢂꢀ  
$
                                                                 
ꢋꢀ  
&/  
Zꢀ  
$
                                                                       
ꢈꢀ  
$
                                                                           
ꢌꢀ  
7ꢀ  
$ꢆꢀ  
                                                                                
$
%
                                                                                     
ꢅꢀ  
/ꢀ  
$ꢁꢀ  
                                                                                          
%
ꢁꢀ  
UH  
2S  
H
W
Jꢀ0  
2'  
(ꢀ  
JꢃꢀD  
G
G
Zꢀ  
Zꢀ  
0
3
%
7
ꢈꢇꢁꢀ  
TABLE 6  
Mode Register Definition  
Field  
BL  
Bits  
Type1) Description  
Burst Length  
[2:0]  
W
Number of sequential bits per DQ related to one read/write command.  
Note: All other bit combinations are RESERVED.  
001B  
010B  
011B  
2
4
8
BT  
CL  
3
Burst Type  
See Table 7 for internal address sequence of low order address bits.  
0 Sequential  
1 Interleaved  
[6:4]  
CAS Latency  
Number of full clocks from read command to first data valid window.  
Note: All other bit combinations are RESERVED.  
010B  
011B  
2
3
110B 2.5  
101B 1.5  
Note: CL = 1.5 for DDR200 components only  
Operating Mode  
MODE [12:7]  
Note: All other bit combinations are RESERVED.  
000000 Normal Operation without DLL Reset  
000010 Normal Operation with DLL Reset  
1) W = write only register bit  
Rev. 1.3, 2006-12  
12  
03292006-W2FE-ELDX