256 Mbit Double Data Rate SDRAM
DDR SDRAM
HYB25D256400B[T/C](L)
HYB25D256800B[T/C](L)
HYB25D256160B[T/C](L)
1
Overview
1.1
Features
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Double data rate architecture: two data transfers per clock cycle.
Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the
receiver.
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DQS is edge-aligned with data for reads and is center-aligned with data for writes
Differential clock inputs (CK and CK)
Four internal banks for concurrent operation
Data mask (DM) for write data
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Burst Lengths: 2, 4, or 8
CAS Latency: 2, 2.5, 3
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
7.8 µs Maximum Average Periodic Refresh Interval (8K refresh)
2.5V (SSTL_2 compatible) I/O
VDDQ = 2.5 V ± 0.2 V (DDR200, DDR266, DDR333); VDDQ = 2.6 V ± 0.1 V (DDR400)
VDD = 2.5 V ± 0.2 V (DDR200, DDR266, DDR333); VDD = 2.6 V ± 0.1 V (DDR400)
P-TSOPII-66-1 package
P-TFBGA-60-2 package with 3 depopulated rows (12 mm × 8 mm2).
Table 1
Performance
Part Number Speed Code
-5
–6
-7F
–7
–8
Unit
—
Speed Grade
Component
DDR400B DDR333B DDR266 DDR266A DDR200
Module
PC3200-
3033
PC2700–
2533
PC2100- PC2100-
PC1600-
2022
—
2022
2033
max. Clock Frequency
@CL3
fCK3 200
166
166
133
–
–
–
MHz
MHz
MHz
@CL2.5 fCK2.5 166
@CL2 fCK2 133
143
133
143
133
125
100
Table 2
1.2
Description
The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits.
It is internally configured as a quad-bank DRAM.
The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data
rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per
clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM effectively consists of a single
2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-
clock-cycle data transfers at the I/O pins.
Data Sheet
6
Rev. 1.21, 2004-07
QIMONDA [ QIMONDA AG ]
