HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Functional Description
T1
T2
T3
T4
T5
T6
CK
CK
Write
NOP
NOP
NOP
PRE
NOP
Command
tWR
BA a, COL b
BA (a or all)
Address
tRP
tDQSS (min)
2
DQS
DQ
DI a-b
1
1
3
4
4
DM
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 1 data element is written.
tWR is referenced from the first positive CK edge after the last desired data in pair.
The Precharge command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
1 = Can be don't care for programmed burst length of 4.
2 = For programmed burst length of 4, DQS becomes don't care at this point.
3 = This bit is correctly written into the memory array if DM is low.
4 = These bits are incorrectly written into the memory array if DM is low.
Don’t Care
Figure 28 Write to Precharge: Minimum DQSS, Odd Number of Data (1-bit Write), Interrupting (Burst
Length = 4 or 8)
Data Sheet
45
Rev. 1.21, 2004-07
02102004-TSR1-4ZWW
QIMONDA [ QIMONDA AG ]
