HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Functional Description
T1
T2
T3
T4
T5
T6
CK
CK
Write
NOP
NOP
NOP
Read
NOP
Command
tWTR
BAa, COL n
BAa, COL b
Address
CL = 2
tDQSS (min)
DQS
DQ
DI a-b
1
2
2
DM
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 3 data elements are written.
2 subsequent elements of data in are applied in the programmed order following DI a-b.
tWTR is referenced from the first positive CK edge after the last desired data in pair (not the last desired data in element)
The Read command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands are not necessarily to the same bank.
1 = This bit is correctly written into the memory array if DM is low.
2 = These bits are incorrectly written into the memory array if DM is low.
Don’t Care
Figure 24 Write to Read: Minimum DQSS, Odd Number of Data (3-bit Write),
Interrupting (CAS Latency = 2; Burst Length = 8)
Data Sheet
41
Rev. 1.21, 2004-07
02102004-TSR1-4ZWW
QIMONDA [ QIMONDA AG ]
