HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Functional Description
Maximum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Write
NOP
NOP
NOP
PRE
NOP
Command
tWR
BA (a or all)
BA a, COL b
Address
tRP
tDQSS (max)
2
DQS
DQ
DI a-b
1
1
3
3
DM
Minimum DQSS
T5 T6
T1
T2
T3
T4
CK
CK
Write
NOP
NOP
NOP
tWR
PRE
NOP
Command
BA a, COL b
BA (a or all)
Address
tRP
tDQSS (min)
2
DQS
DQ
DI a-b
3
3
1
1
DM
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 2 data elements are written.
1 subsequent element of data in is applied in the programmed order following DI a-b.
tWR is referenced from the first positive CK edge after the last desired data in pair.
The Precharge command masks the last 2 data elements in the burst, for burst length = 8.
A10 is Low with the Write command (Auto Precharge is disabled).
1 = Can be don't care for programmed burst length of 4.
2 = For programmed burst length of 4, DQS becomes don't care at this point.
3 = These bits are incorrectly written into the memory array if DM is low.
Don’t Care
Figure 27 Write to Precharge: Interrupting (Burst Length = 4 or 8)
Data Sheet
44
Rev. 1.21, 2004-07
02102004-TSR1-4ZWW
QIMONDA [ QIMONDA AG ]
