Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
TABLE 19
AC Operating Conditions
Parameter
Symbol
Values
Max.
Unit Note1)/ Test
Condition
Min.
2)3)
Input High (Logic 1) Voltage, DQ, DQS and DM Signals
Input Low (Logic 0) Voltage, DQ, DQS and DM Signals
Input Differential Voltage, CK and CK Inputs
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
V
REF + 0.31
—
V
—
0.7
V
V
REF – 0.31
DDQ + 0.6
V
V
V
—
4)
5)
Input Closing Point Voltage, CK and CK Inputs
0.5 × VDDQ
–
0.5 × VDDQ+
0.2
0.2
1)
VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR200 - DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400); 0 °C ≤ TA ≤ 70 °C
2) Input slew rate = 1 V/ns.
3) Inputs are not recognized as valid until VREF stabilizes.
4)
VID is the magnitude of the difference between the input level on CK and the input level on CK.
5) The value of VIX is expected to equal 0.5 × VDDQ of the transmitting device and must track variations in the DC level of the same.
TABLE 20
IDD Conditions
Parameter
Symbol
Operating Current: one bank; active/ precharge; tRC = tRCMIN; tCK = tCKMIN
;
IDD0
DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two
clock cycles.
Operating Current: one bank; active/read/precharge; Burst = 4;
Refer to the following page for detailed test conditions.
IDD1
Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE ≤ VILMAX; tCK = tCKMIN
IDD2P
IDD2F
Precharge Floating Standby Current: CS ≥ VIHMIN, all banks idle;
CKE ≥ VIHMIN; tCK = tCKMIN, address and other control inputs changing once per clock cycle, VIN = VREF for DQ, DQS
and DM.
Precharge Quiet Standby Current:CS ≥ VIHMIN, all banks idle; CKE ≥ VIHMIN; tCK = tCKMIN, address and other control IDD2Q
inputs stable at ≥ VIHMIN or ≤ VILMAX; VIN = VREF for DQ, DQS and DM.
Active Power-Down Standby Current: one bank active; power-down mode;
IDD3P
CKE ≤ VILMAX; tCK = tCKMIN; VIN = VREF for DQ, DQS and DM.
Active Standby Current: one bank active; CS ≥ VIHMIN; CKE ≥ VIHMIN; tRC = tRASMAX; tCK = tCKMIN; DQ, DM and DQS IDD3N
inputs changing twice per clock cycle; address and control inputs changing once per clock cycle.
Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs changing once IDD4R
per clock cycle; 50 % of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A, CL = 3
for DDR333; tCK = tCKMIN; IOUT = 0 mA
Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs changing once IDD4W
per clock cycle; 50 % of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A, CL = 3
for DDR333; tCK = tCKMIN
Auto-Refresh Current: tRC = tRFCMIN, burst refresh
IDD5
IDD6
IDD7
Self-Refresh Current: CKE ≤ 0.2 V; external clock on; tCK = tCKMIN
Operating Current: four bank; four bank interleaving with BL = 4; Refer to the following page for detailed test
conditions.
Rev. 1.6, 2007-02
24
03292006-U5AN-6TI1
QIMONDA [ QIMONDA AG ]
