Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
TABLE 17
Input and Output Capacitances
Parameter
Symbol
Values
Typ.
Unit
Note/
Test Condition
Min.
Max.
Input Capacitance: CK, CK
CI1
1.5
2.0
—
—
—
—
—
—
—
2.5
3.0
0.25
2.5
3.0
0.5
pF
pF
pF
pF
pF
pF
P(G)-TFBGA-60 1)
P(G)-TSOPII-66
—
Delta Input Capacitance
CdI1
CI2
Input Capacitance: All other input-only pins
1.5
2.0
—
P(G)-TFBGA-60
P(G)-TSOPII-66
—
Delta Input Capacitance: All other input-only CdIO
pins
Input/Output Capacitance: DQ, DQS, DM
CIO
3.5
4.0
—
—
—
—
4.5
5.0
0.5
pF
pF
pF
P(G)-TFBGA-60 2)
P(G)-TSOPII-66
—
Delta Input/Output Capacitance: DQ, DQS,
DM
CdIO
1) These values are not subject to production test - verified by design/characterization and are tested on a sample base only. VDDQ = VDD
2.5 V ± 0.2 V, f = 100 MHz, TA = 25 °C, VOUT(DC) = VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins are tied to ground.
=
2) DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the
board level.
Rev. 1.6, 2007-02
21
03292006-U5AN-6TI1
QIMONDA [ QIMONDA AG ]
