Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
TABLE 22
AC Timing - Absolute Specifications
Parameter
Symbol –5
DDR400B
–6
Unit Note1)/ Test
Condition
DDR333
Min.
Min.
Max.
Max.
2)3)4)5)
DQ output access time from CK/CK tAC
–0.5
+0.5
0.55
8
–0.7
+0.7
0.55
12
ns
tCK
ns
ns
ns
tCK
tCK
CK high-level width
Clock cycle time
tCH
tCK
0.45
0.45
—
5
6
CL = 3.0
CL = 2.5
CL = 2.0
6
12
6
12
7.5
12
7.5
12
CK low-level width
tCL
0.45
0.55
)
0.45
0.55
)
—
6)
Auto precharge write recovery +
precharge time
tDAL
(tWR/tCK)+(tRP/tCK
(tWR/tCK)+(tRP/tCK
DQ and DM input hold time
tDH
0.4
—
—
0.45
1.75
—
—
ns
ns
—
—
DQ and DM input pulse width (each tDIPW
1.75
input)
DQS output access time from CK/CK tDQSCK
–0.5
0.35
+0.5
—
–0.6
0.35
+0.6
—
ns
—
—
DQS input low (high) pulse width
(write cycle)
tDQSL,H
tCK
DQS-DQ skew (DQS and associated tDQSQ
DQ signals)
—
+0.40
+0.40
1.25
—
—
+0.40 ns
+0.45 ns
TFBGA
TSOPII
—
DQS-DQ skew (DQS and associated tDQSQ
DQ signals)
Write command to 1st DQS latching tDQSS
—
0.72
0.75
1.25
tCK
transition
DQ and DM input setup time
tDS
0.4
0.2
—
—
0.45
0.2
—
—
ns
—
—
DQS falling edge hold time from CK tDSH
tCK
(write cycle)
DQS falling edge to CK setup time
(write cycle)
tDSS
tHP
0.2
—
0.2
—
tCK
—
Clock Half Period
min. (tCL, tCH
)
—
min. (tCL, tCH
)
—
ns
ns
—
7)
Data-out high-impedance time from tHZ
—
+0.7
–0.7
+0.7
CK/CK
Address and control input hold time tIH
0.6
0.7
2.2
0.6
0.7
—
—
—
—
—
0.75
0.8
—
—
—
—
—
ns
ns
ns
ns
ns
fast slew rate
8)
slow slew rate
9)
Control and Addr. input pulse width
(each input)
tIPW
2.2
Address and control input setup time tIS
0.75
0.8
fast slew rate
slow slew rate
Rev. 1.6, 2007-02
26
03292006-U5AN-6TI1
QIMONDA [ QIMONDA AG ]
