欢迎访问ic37.com |
会员登录 免费注册
发布采购

HYB18T256400BF-3.7 参数 Datasheet PDF下载

HYB18T256400BF-3.7图片预览
型号: HYB18T256400BF-3.7
PDF下载: 下载PDF文件 查看货源
内容描述: 256兆位双数据速率 - 双SDRAM的 [256-Mbit Double-Data-Rate-Two SDRAM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 71 页 / 4102 K
品牌: QIMONDA [ QIMONDA AG ]
 浏览型号HYB18T256400BF-3.7的Datasheet PDF文件第50页浏览型号HYB18T256400BF-3.7的Datasheet PDF文件第51页浏览型号HYB18T256400BF-3.7的Datasheet PDF文件第52页浏览型号HYB18T256400BF-3.7的Datasheet PDF文件第53页浏览型号HYB18T256400BF-3.7的Datasheet PDF文件第55页浏览型号HYB18T256400BF-3.7的Datasheet PDF文件第56页浏览型号HYB18T256400BF-3.7的Datasheet PDF文件第57页浏览型号HYB18T256400BF-3.7的Datasheet PDF文件第58页  
Internet Data Sheet  
HY[B/I]18T256[40/80/16]0B[C/F](L)  
256-Mbit Double-Data-Rate-Two SDRAM  
TABLE 54  
DRAM Component Timing Parameter by Speed Grade - DDR2–533  
Parameter  
Symbol  
DDR2–533  
Unit  
Notes1)2)3)4)5)  
6)  
Min.  
Max.  
DQ output access time from CK / CK  
CAS A to CAS B command period  
CK, CK high-level width  
tAC  
–500  
2
+500  
ps  
tCCD  
tCH  
tCKE  
tCL  
tCK  
tCK  
tCK  
tCK  
tCK  
0.45  
3
0.55  
CKE minimum high and low pulse width  
CK, CK low-level width  
0.45  
WR + tRP  
0.55  
7)17)  
8)  
Auto-Precharge write recovery + precharge  
time  
tDAL  
Minimum time clocks remain ON after CKE  
asynchronously drops LOW  
tDELAY  
tIS + tCK + tIH  
225  
––  
––  
ns  
ps  
ps  
9)  
DQ and DM input hold time (differential data  
strobe)  
t
t
DH(base)  
10)  
DQ and DM input hold time (single ended data  
strobe)  
DH1(base)  
–25  
DQ and DM input pulse width (each input)  
DQS output access time from CK / CK  
tDIPW  
0.35  
–450  
0.35  
tCK  
ps  
tCK  
ps  
tDQSCK  
+450  
DQS input low (high) pulse width (write cycle) tDQSL,H  
10)  
DQS-DQ skew (for DQS & associated DQ  
signals)  
tDQSQ  
300  
Write command to 1st DQS latching transition tDQSS  
– 0.25  
100  
+ 0.25  
tCK  
10)  
10)  
DQ and DM input setup time (differential data  
strobe)  
t
DS(base)  
ps  
DQ and DM input setup time (single ended data tDS1(base)  
strobe)  
–25  
0.2  
ps  
DQS falling edge hold time from CK (write  
cycle)  
tDSH  
tCK  
tCK  
DQS falling edge to CK setup time (write cycle) tDSS  
0.2  
11)  
12)  
10)  
Clock half period  
tHP  
MIN. (tCL, tCH)  
Data-out high-impedance time from CK / CK  
Address and control input hold time  
tHZ  
tAC.MAX  
ps  
ps  
tCK  
tIH(base)  
tIPW  
375  
0.6  
Address and control input pulse width  
(each input)  
10)  
13)  
13)  
Address and control input setup time  
DQ low-impedance time from CK / CK  
DQS low-impedance from CK / CK  
MRS command to ODT update delay  
Mode register set command cycle time  
OCD drive mode output delay  
tIS(base)  
tLZ(DQ)  
tLZ(DQS)  
tMOD  
250  
ps  
ps  
ps  
ns  
tCK  
ns  
2 × tAC.MIN  
tAC.MAX  
tAC.MAX  
12  
tAC.MIN  
0
2
0
tMRD  
tOIT  
12  
Data output hold time from DQS  
Data hold skew factor  
tQH  
t
HP tQHS  
tQHS  
400  
ps  
Rev. 1.11, 2007-07  
54  
11172006-LBIU-F1TN  
 复制成功!