Internet Data Sheet
HY[B/I]18T256[40/80/16]0B[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol
DDR2–533
Min.
Unit
Notes1)2)3)4)5)
6)
Max.
13)14)
15)17)
16)
Average periodic refresh Interval
Average periodic refresh Interval
tREFI
tREFI
tRFC
—
—
75
7.8
3.9
—
μs
μs
ns
Auto-Refresh to Active/Auto-Refresh
command period
Precharge-All (4 banks) command period
Read preamble
tRP
tRP
—
ns
tCK
tCK
ns
13)
tRPRE
tRPST
tRRD
0.9
0.40
7.5
1.1
0.60
—
13)
Read postamble
13)17)
Active bank A to Active bank B command
period
15)21)
Active bank A to Active bank B command
period
tRRD
10
—
ns
Internal Read to Precharge command delay
Write preamble
tRTP
7.5
—
ns
tCK
tCK
ns
tWPRE
tWPST
tWR
0.25
0.40
15
—
18)
Write postamble
0.60
—
Write recovery time for write without Auto-
Precharge
19)
20)
Internal Write to Read command delay
tWTR
7.5
2
—
—
ns
Exit power down to any valid command
(other than NOP or Deselect)
tXARD
tCK
20)
Exit active power-down mode to Read
command (slow exit, lower power)
tXARDS
tXP
6 – AL
2
—
—
tCK
tCK
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
tXSNR
tXSRD
WR
t
RFC +10
200
WR/tCK
—
—
ns
tCK
tCK
21)
Write recovery time for write with Auto-
Precharge
t
1)
VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V.
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other Slew Rates see Chapter 8 of this
datasheet.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode. The input reference level for signals other than CK/CK, DQS/DQS,
RDQS / RDQS is defined in Chapter 8.3 of this datasheet.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
6) The output timing reference voltage level is VTT. See Chapter 8 for the reference load for timing measurements.
7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
9) For timing definition, refer to the Component data sheet.
10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
11) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
Rev. 1.11, 2007-07
55
11172006-LBIU-F1TN
QIMONDA [ QIMONDA AG ]
