Internet Data Sheet
HY[B/I]18T256[40/80/16]0B[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol
DDR2–667
Min.
Unit
Notes1)2)3)4)5)6)
7)
Max.
26)
DQ hold skew factor
tQHS
tREFI
—
—
—
75
340
7.8
3.9
—
ps
μs
μs
ns
27)28)
28)29)
30)
Average periodic refresh Interval
Auto-Refresh to Active/Auto-Refresh command tRFC
period
Precharge-All (4 banks) command period
Read preamble
tRP
tRP
—
ns
31)32)
31)33)
34)
tRPRE
tRPST
tRTP
0.9
0.4
7.5
0.35
0.4
15
1.1
0.6
—
tCK.AVG
tCK.AVG
ns
Read postamble
Internal Read to Precharge command delay
Write preamble
tWPRE
tWPST
tWR
—
tCK.AVG
tCK.AVG
ns
Write postamble
0.6
—
34)
Write recovery time
34)35)
Internal write to read command delay
Exit power down to read command
tWTR
tXARD
7.5
2
—
ns
—
nCK
nCK
Exit active power-down mode to read command tXARDS
7 – AL
—
(slow exit, lower power)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
tXP
2
—
nCK
34)
Exit self-refresh to a non-read command
Exit self-refresh to read command
tXSNR
tXSRD
t
RFC +10
—
—
ns
200
nCK
nCK
Write command to DQS associated clock edges WL
DDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V.
RL–1
1)
V
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other Slew Rates see Chapter 8 of this
datasheet.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode. The input reference level for signals other than CK/CK, DQS/DQS,
RDQS / RDQS is defined in Chapter 8.3 of this datasheet.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
6) The output timing reference voltage level is VTT. See Chapter 8 for the reference load for timing measurements.
7) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min)
.
8) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272
ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and
t
DQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED)
= - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
9) Input clock jitter spec parameter. These parameters and the ones in Chapter 7.3 are referred to as 'input clock jitter spec parameters' and
these parameters apply to DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
10) These parameters are specified per their average values, however it is understood that the relationship as defined in Chapter 7.3 between
the average timing and the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations
of Chapter 7.3).
Rev. 1.11, 2007-07
50
11172006-LBIU-F1TN
QIMONDA [ QIMONDA AG ]
