UH
JꢍꢌD
GGUꢌ
0
3
%
7ꢀ
ꢃꢀꢀꢌ
Internet Data Sheet
HYB18TC512[80/16]0BF
512-Mbit Double-Data-Rate-Two SDRAM
%
$
ꢈꢌ %
$
ꢅꢌ %
$
ꢀꢌ $
ꢅ
ꢆꢌ $
ꢅ
ꢈꢌ $
ꢅꢅ
ꢌ $
ꢅ
ꢀꢌ
$
ꢉꢌ
$
ꢊꢌ
$
ꢇꢌ
ꢀꢌ
$ꢂꢌ
$
ꢁꢌ
$
ꢃꢌ
$
ꢆꢌ
$ꢈꢌ
$
ꢅꢌ
$ꢀꢌ
ꢀꢌ
ꢅꢌ
ꢅꢌ
TABLE 17
EMR(3) Programming Extended Mode Register Definition(BA[2:0]=011B)
Field
Bits
Type1)
Description
BA2
16
reg.addr
Bank Address[2]
Note: BA2 is not available on 256Mbit and 512Mbit components
0B
BA2 Bank Address
BA1
BA0
A
15
Bank Adress[1]
1B
BA1 Bank Address
14
Bank Adress[0]
1B
BA0 Bank Address
[13:0]
w
Address Bus[13:0]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
00000000000000BA[13:0] Address bits
1) w = write only
TABLE 18
Burst Length and Sequence
Burst Length
Starting Address
(A2 A1 A0)
Sequential Addressing
(decimal)
Interleave Addressing
(decimal)
4
× 0 0
× 0 1
×1 0
0, 1, 2, 3
0, 1, 2, 3
1, 2, 3, 0
1, 0, 3, 2
2, 3, 0, 1
2, 3, 0, 1
×1 1
3, 0, 1, 2
3, 2, 1, 0
8
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
Rev. 1.21, 2007-09
20
03292006-HDLH-OAY6
QIMONDA [ QIMONDA AG ]
