U
HJ
ꢍꢌD
G
G
Uꢌ
Zꢌ
Zꢌ
Zꢌ
Zꢌ
Zꢌ
Zꢌ
Zꢌ
Zꢌ
0
3
%
7ꢀ
ꢆꢊꢀꢌ
Internet Data Sheet
HYB18TC512[80/16]0BF
512-Mbit Double-Data-Rate-Two SDRAM
%
$
ꢈꢌ %
$
ꢅꢌ %
$
ꢀꢌ $
ꢅ
ꢆꢌ $
4ꢌ I 5'
ꢀꢌ
ꢅ
ꢈꢌ $
ꢅꢅ
ꢌ $
ꢅ
ꢀꢌ
$
ꢉꢌ
&'
$
ꢊꢌ
$
ꢇꢌ
$
ꢂꢌ
$
ꢁꢌ
$
ꢃꢌ
/ꢌ
$
ꢆꢌ
$
ꢈꢌ
$
ꢅꢌ
$
ꢀꢌ
/ꢌ
2
ꢌ
3U
R
J
U
DPꢌ
ꢀꢌ
4
6ꢌ '4
6
ꢌ
5ꢌW
$
5ꢌW
',&ꢌ '/
ꢀꢌ
ꢅꢌ
Wꢀ
Wꢀ
RI ꢀ
TABLE 15
Extended Mode Register Definition (BA[2:0] = 001B)
Field
Bits
Type1)
Description
Bank Address [2]
Note: BA2 not available on 256 Mbit and 512 Mbit components
0B BA2 Bank Address
Bank Address [1]
BA2
16
reg. addr.
BA1
BA0
A13
15
14
13
0B
BA1 Bank Address
Bank Address [0]
1B
BA0 Bank Address
w
Address Bus [13]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
0B
A13 Address bit 13
Qoff
12
w
w
w
w
Output Disable
0B
1B
QOff Output buffers enabled
QOff Output buffers disabled
RDQS
DQS
OCD
11
Read Data Strobe Output (RDQS, RDQS)
0B
1B
RDQS Disable
RDQS Enable
10
Complement Data Strobe (DQS Output)
0B
1B
DQS Enable
DQS Disable
[9:7]
Off-Chip Driver Calibration Program
000B OCD OCD calibration mode exit, maintain setting
001B OCD Drive (1)
Program
010B OCD Drive (0)
100B OCD Adjust mode
111B OCD OCD calibration default
AL
[5:3]
w
Additive Latency
Note: All other bit combinations are illegal.
000B AL 0
001B AL 1
010B AL 2
011B AL 3
100B AL 4
101B AL 5
Rev. 1.21, 2007-09
17
03292006-HDLH-OAY6
QIMONDA [ QIMONDA AG ]
