Internet Data Sheet
HYB18TC256[80/16]0BF
256-Mbit Double-Data-Rate-Two SDRAM
Example: for DDR2-667, tCH.ABS(Min) = (0.48 x 3000ps) – 125 ps = 1315 ps = 0.438 x 3000 ps.
Table 64 shows clock-jitter specifications.
TABLE 52
Clock-Jitter Specifications for –667 and –800
Symbol
Parameter
DDR2 -667
DDR2 -800
Unit
Min.
Max.
Min.
Max.
tCK.AVG
Average clock period nominal w/o jitter
Clock-period jitter
3000
–125
–100
–250
–200
8000
+125
+100
+250
+200
2500
–100
–80
8000
+100
+80
ps
ps
ps
ps
ps
tJIT.PER
tJIT(PER,LCK)
tJIT.CC
Clock-period jitter during DLL locking period
Cycle-to-cycle clock-period jitter
–200
–160
+200
+160
tJIT(CC,LCK)
Cycle-to-cycle clock-period jitter during DLL-
locking period
tERR.2PER
tERR.3PER
tERR.4PER
tERR.5PER
tERR(6-10PER)
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
–175
–225
–250
–250
–350
+175
+225
+250
+250
+350
–150
–175
–200
–200
–300
+150
+175
+200
+200
+300
ps
ps
ps
ps
ps
Cumulative error across n cycles with n = 6 ..
10, inclusive
tERR(11-50PER)
Cumulative error across n cycles with n = 11 .. –450
50, inclusive
+450
–450
+450
ps
tCH.AVG
tCL.AVG
tJIT.DUTY
Average high-pulse width
Average low-pulse width
Duty-cycle jitter
0.48
0.48
–125
0.52
0.52
+125
0.48
0.48
–100
0.52
0.52
+100
tCK.AVG
tCK.AVG
ps
Rev. 1.3, 2007-05
52
07182006-DD60-22E6
QIMONDA [ QIMONDA AG ]
