Internet Data Sheet
HYB18TC256[80/16]0BF
256-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol
DDR2–400
Unit
Note1)2)3)4)5)
6)
Min.
Max.
DQS falling edge hold time from CK (write
cycle)
tDSH
0.2
—
tCK
DQS falling edge to CK setup time (write cycle) tDSS
0.2
—
tCK
—
11)
12)
10)
Clock half period
tHP
MIN. (tCL, tCH)
Data-out high-impedance time from CK / CK
Address and control input hold time
tHZ
—
tAC.MAX
—
ps
ps
tCK
tIH(base)
tIPW
475
0.6
Address and control input pulse width
(each input)
—
10)
13)
13)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
MRS command to ODT update delay
Mode register set command cycle time
OCD drive mode output delay
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMOD
350
—
ps
ps
ps
ns
tCK
ns
—
ps
µs
µs
ns
2 × tAC.MIN
tAC.MAX
tAC.MAX
12
tAC.MIN
0
2
0
tMRD
—
tOIT
12
Data output hold time from DQS
Data hold skew factor
tQH
t
HP –tQHS
—
tQHS
—
—
450
7.8
3.9
—
13)14)
15)17)
16)
Average periodic refresh Interval
Average periodic refresh Interval
tREFI
tREFI
—
Auto-Refresh to Active/Auto-Refresh
command period
tRFC
75
Precharge-All (4 banks) command period
Read preamble
tRP
tRP
—
ns
tCK
tCK
ns
13)
tRPRE
tRPST
tRRD
0.9
0.40
7.5
1.1
0.60
—
13)
Read postamble
13)17)
Active bank A to Active bank B command
period
15)21)
Active bank A to Active bank B command
period
tRRD
10
—
ns
Internal Read to Precharge command delay
Write preamble
tRTP
7.5
—
ns
tCK
tCK
ns
tWPRE
tWPST
tWR
0.25
0.40
15
—
18)
Write postamble
0.60
—
Write recovery time for write without Auto-
Precharge
19)
20)
Internal Write to Read command delay
tWTR
10
2
—
—
ns
Exit power down to any valid command
(other than NOP or Deselect)
tXARD
tCK
20)
Exit active power-down mode to Read
command (slow exit, lower power)
tXARDS
tXP
6 – AL
2
—
—
—
tCK
tCK
ns
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit Self-Refresh to non-Read command
tXSNR
tRFC +10
Rev. 1.3, 2007-05
48
07182006-DD60-22E6
QIMONDA [ QIMONDA AG ]
