Internet Data Sheet
HYB18TC256[80/16]0BF
256-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol Note
1)2)3)4)5)6)
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating, Data
bus inputs are floating.
1)2)3)4)5)6)7)
Operating Bank Interleave Read Current
IDD7
All banks interleaving reads, IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) -1 × tCK(IDD); tCK = tCK(IDD)
,
t
RC = tRC(IDD), tRRD = tRRD(IDD); CKE is HIGH, CS is HIGH between valid commands. Address bus inputs
are stable during deselects; Data pattern is same as IDD4R;
Refer to the following pages for detailed timing conditions
1)
2)
3)
VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
IDD specifications are tested after the device is properly initialized.
DD parameter are specified with ODT disabled.
I
4) Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS.
5) For IDD definition see Table 40
6) Timing parameter minimum and maximum values for IDD current measurements are defined in Chapter 7.
7) A - Activate, RA - Read with Auto-Precharge, D - Deselect
TABLE 40
Definition for IDD
Parameter
Description
LOW
Defined as VIN ≤ VIL(AC).MAX
HIGH
Defined as VIN ≥ VIH(AC).MIN
STABLE
FLOATING
SWITCHING
Defined as inputs are stable at a HIGH or LOW level
Defined as inputs are VREF = VDDQ / 2
Defined as: Inputs are changing between high and low every other clock (once per two clocks) for address
and control signals, and inputs changing between high and low every other clock (once per clock) for DQ
signals not including mask or strobes
Detailed IDD7
The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the
specification.
Legend: A - Active; RA - Read with Autoprecharge; D - Deselect
IDD7: Operating Current: All Bank Interleave Read operation
All banks are being interleaved at minimum tRC(IDD) without violating tRRD(IDD) and ttFAW(IDD) using a burst length of 4. Control
and address bus inputs are STABLE during Deselect. IOUT = 0 mA
Timing Patterns for 4 bank devices with 1 KB or 2 KB page size
-DDR2-400 4-4-4: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D D
-DDR2-400 3-3-3: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D
-DDR2-533 4-4-4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
-DDR2-533 3-3-3: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D
-DDR2-667 5-5-5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D
-DDR2-667 4-4-4: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D
-DDR2-800 6-6-6: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D D
-DDR2-800 5-5-5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D
Rev. 1.3, 2007-05
32
07182006-DD60-22E6
QIMONDA [ QIMONDA AG ]
