Internet Data Sheet
HYB18TC256[80/16]0BF
256-Mbit Double-Data-Rate-Two SDRAM
TABLE 34
OCD Default Characteristics
Symbol
Description
Min.
Nominal
Max.
Unit
Note
1)2)
—
—
—
Output Impedance
See Chapter 5.5
Ω
Ω
Ω
1)2)3)
4)
Pull-up / Pull down mismatch
0
0
—
—
4
Output Impedance step size
for OCD calibration
1.5
1)5)6)7)
SOUT
Output Slew Rate
1.5
—
5.0
V / ns
1)
VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) Impedance measurement condition for output source dc current: VDDQ = 1.7 V, VOUT = 1420 mV; (VOUT–VDDQ) / IOH must be less than
23.4 Ohm for values of VOUT between VDDQ and VDDQ – 280 mV. Impedance measurement condition for output sink dc current:
VDDQ = 1.7 V; VOUT = –280 mV; VOUT / IOL must be less than 23.4 Ohms for values of VOUT between 0 V and 280 mV.
3) Mismatch is absolute value between pull-up and pull-down, both measured at same temperature and voltage.
4) This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and represents only the
DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18 ± 0.75 Ohms under nominal
conditions.
5) The absolute value of the Slew Rate as measured from DC to DC is equal to or greater than the Slew Rate as measured from AC to AC.
This is verified by design and characterization but not subject to production test.
6) Timing skew due to DRAM output Slew Rate mis-match between DQS / DQS and associated DQ’s is included in tDQSQ and tQHS
specification.
7) DRAM output Slew Rate specification applies to 400, 533 and 667 MT/s speed bins.
Rev. 1.3, 2007-05
28
07182006-DD60-22E6
QIMONDA [ QIMONDA AG ]
