UH
JꢍꢌD
GGUꢌ
0
3
%
7ꢀ
ꢃꢀꢀꢌ
Internet Data Sheet
HYB18TC1G[80/16]0AF
1-Gbit DDR2 SDRAM
%
$
ꢇꢌ %
$
ꢁꢌ %
$
ꢀꢌ $
ꢁ
ꢅꢌ $
ꢁ
ꢇꢌ $
ꢁꢁ
ꢌ $
ꢁ
ꢀꢌ
$
ꢉꢌ
$
ꢊꢌ
$
ꢆꢌ
ꢀꢌ
$ꢂꢌ
$
ꢈꢌ
$
ꢃꢌ
$
ꢅꢌ
$ꢇꢌ
$
ꢁꢌ
$ꢀꢌ
ꢀꢌ
ꢁꢌ
ꢁꢌ
TABLE 14
EMR(3) Programming Extended Mode Register Definition (BA[2:0]=010B)
Field
Bits
Type1)
Description
BA2
16
reg.addr
Bank Address[2]
Note: BA2 is not available on 256 Mbit and 512 Mbit components
0B
BA2 Bank Address
BA1
BA0
A
15
Bank Adress[1]
1B
BA1 Bank Address
14
Bank Adress[0]
1B
BA0 Bank Address
[13:0]
w
Address Bus[13:0]
Note: A13 is not available for 256 Mbit and ×16 512 Mbit configuration
0B
A[13:0] Address bits
1) w = write only
Rev. 1.11, 2006-09
18
03292006-PJAE-UQLG
QIMONDA [ QIMONDA AG ]
