Internet Data Sheet
HYB18TC1G[80/16]0AF
1-Gbit DDR2 SDRAM
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TABLE 13
EMRS(2) Programming Extended Mode register Definition (BA[2:0]=010B)
Field Bits
Type1)
Description
BA2
16
w
Bank Address[2]
Note: BA2 is not available on 256 Mbit and 512 Mbit components
0B
BA2 Bank Address
BA
[15:14]
w
Bank Adress[15:14]
00B BA MRS
01B BA EMRS(1)
10B BA EMRS(2)
11B BA EMRS(3): Reserved
A
A
[13:7]
7
w
w
Address Bus[13:0]
Note: A13 is not available for 256 Mbit and ×16 512 Mbit configuration
0B
A[13:0] Address bits
Address Bus[7], adapted self refresh rate for TCASE > 85°C
0B
1B
A7 disable
A7 enable 2)
A
A
[6:4]
3
w
w
Address Bus[6:4]
0B
A[6:4] Address bits
Address Bus[3], Duty Cycle Correction (DCC)
0B
1B
A[3] DCC disabled
A[3] DCC enabled
Partial Self Refresh for 8 banks
[2:0]
A
w
Address Bus[2:0], Partial Array Self Refresh for 8 Banks3)
000B PASR0 Full Array
001B PASR1 Half Array (BA[2:0]=000, 001, 010 & 011)
010B PASR2 Quarter Array (BA[2:0]=000, 001)
011B PASR3 1/8 array (BA[2:0] = 000)
100B PASR4 3/4 array (BA[2:0]= 010, 011, 100, 101, 110 & 111)
101B PASR5 Half array (BA[2:0]=100, 101, 110 & 111)
110B PASR6 Quarter array (BA[2:0]= 110 & 111)
111B PASR7 1/8 array(BA[2:0]=111)
1) w = write only
2) When DRAM is operated at 85°C ≤ TCase ≤ 95°C the extended self refresh rate must be enabled by setting bit A7 to "1" before the self
refresh mode can be entered.
3) If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost if self refresh
is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued
Rev. 1.11, 2006-09
17
03292006-PJAE-UQLG
QIMONDA [ QIMONDA AG ]
