Internet Data Sheet
HYB18TC1G[80/16]0AF
1-Gbit DDR2 SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
Data Signals ×16 Organization
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
DQ0
DQ1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Signal 15:0
Note: Bi-directional data bus. DQ[15:0] for ×16 components.
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Data Strobe ×16 Organization
B7
A8
F7
E8
UDQS
UDQS
LDQS
LDQS
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
Data Strobe Upper Byte
Data Strobe Lower Byte
Data Mask ×16 Organization
B3
F3
UDM
LDM
I
I
SSTL
SSTL
Data Mask Upper Byte
Data Mask Lower Byte
Power Supplies ×16 Organization
J2
VREF
AI
–
–
I/O Reference Voltage
E9, G1, G3, G7, VDDQ
PWR
I/O Driver Power Supply
G9
J1
VDDL
PWR
PWR
PWR
–
–
–
Power Supply
Power Supply
Power Supply
E1, J9, M9, R1 VDD
E7, F2, F8, H2, VSSQ
H8
J7
VSSDL
VSS
PWR
PWR
–
–
Power Supply
Power Supply
J3,N1,P9
Not Connected ×16 Organization
A2, E2, L1, R3, NC
R7, R8
NC
–
Not Connected
Other Pins ×16 Organization
K9 ODT
I
SSTL
On-Die Termination Control
Rev. 1.11, 2006-09
11
03292006-PJAE-UQLG