Internet Data Sheet
HYB18TC1G[80/16]0AF
1-Gbit DDR2 SDRAM
2
Pin Configuration
This chapter contains the pin configuration.
2.1
Pin Configuration for TFBGA–68
The pin configuration of a DDR2 SDRAM is listed by function in Table 5. The abbreviations used in the Pin# and Buffer Type
columns are explained in Table 6 and Table 7 respectively. The pin numbering for the FBGA package is depicted in Figure 1
for ×8 components.
TABLE 5
Pin Configuration of DDR2 SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
Clock Signals ×8 Organizations
J8
CK
I
I
I
SSTL
SSTL
SSTL
Clock Signal CK, Complementary Clock Signal CK
Clock Enable
K8
K2
CK
CKE
Control Signals ×8 Organizations
K7
L7
K3
L8
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
CS
Chip Select
Address Signals ×8 Organizations
L2
BA0
BA1
BA2
A0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Bank Address Bus 2:0
L3
L1
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
Address Signal 12:0, Address Signal 10/Autoprecharge
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
P7
R2
Rev. 1.11, 2006-09
6
03292006-PJAE-UQLG
QIMONDA [ QIMONDA AG ]
