Internet Data Sheet
HYB18TC1G[80/16]0AF
1-Gbit DDR2 SDRAM
2.2
Pin Configuration for TFBGA-92
The pin configuration of a DDR2 SDRAM is listed by function in Table 8. The abbreviations used in the Pin#/Buffer Type
columns are explained in Table 9 and Table 10 respectively. The pin numbering for the FBGA package is depicted in Figure 2
for ×16 components.
TABLE 8
Pin Configuration of DDR SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
Clock Signals ×16 Organization
J8
CK
I
I
I
SSTL
SSTL
SSTL
Clock Signal CK, Complementary Clock Signal CK
Clock Enable
K8
K2
CK
CKE
Control Signals ×16 Organization
K7
L7
K3
L8
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
CS
Chip Select
Address Signals ×16 Organization
L2
L3
L1
BA0
BA1
BA2
I
I
I
SSTL
SSTL
SSTL
Bank Address Bus 1:0
Bank Address Bus 2
Note: 1 Gbit components and higher
Note: 256 Mbit and 512 Mbit components
Address Signal 12:0,Address Signal 10/Autoprecharge
NC
A0
–
I
I
I
I
I
I
I
I
I
I
I
I
I
I
–
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
P7
R2
Rev. 1.11, 2006-09
10
03292006-PJAE-UQLG
QIMONDA [ QIMONDA AG ]
