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Internet Data Sheet
HYB18T512[40/80/16]0B[C/F]
512-Mbit Double-Data-Rate-Two SDRAM
Field
Bits
Type1)
Description
CL
[6:4]
w
CAS Latency
Note: All other bit combinations are illegal.
011B CL 3
100B CL 4
101B CL 5
110B CL 6
111B CL 7
BT
BL
3
w
w
Burst Type
0B
1B
BT Sequential
BT Interleaved
[2:0]
Burst Length
Note: All other bit combinations are illegal.
010B BL 4
011B BL 8
1) w = write only register bits
2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and
rounding up to the next integer: WR [cycles] ≥ tWR (ns) / tCK (ns). The mode register must be programmed to fulfill the minimum requirement
for the analogue tWR timing WRMIN is determined by tCK.MAX and WRMAX is determined by tCK.MIN
.
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TABLE 14
Extended Mode Register Definition (BA[2:0] = 001B)
Field
Bits
Type1)
Description
Bank Address [2]
Note: BA2 not available on 256 Mbit and 512 Mbit components
0B BA2 Bank Address
Bank Address [1]
BA2
16
reg. addr.
BA1
BA0
A13
15
14
13
0B
BA1 Bank Address
Bank Address [0]
1B
BA0 Bank Address
w
Address Bus [13]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
0B
A13 Address bit 13
Qoff
12
11
w
w
Output Disable
0B
1B
QOff Output buffers enabled
QOff Output buffers disabled
RDQS
Read Data Strobe Output (RDQS, RDQS)
0B
1B
RDQS Disable
RDQS Enable
Rev. 1.1, 2007-05
19
03292006-YBYM-WG0Z
QIMONDA [ QIMONDA AG ]
