Internet Data Sheet
HY[B/I]18T512[40/80/16]0B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
5.3
DC & AC Characteristics
DDR2 SDRAM pin timing are specified for either single ended
or differential mode depending on the setting of the EMRS(1)
“Enable DQS” mode bit; timing advantages of differential
mode are realized in system design. The method by which the
DDR2 SDRAM pin timing are measured is mode dependent.
In single ended mode, timing relationships are measured
In differential mode, these timing relationships are measured
relative to the crosspoint of DQS and its complement, DQS.
This distinction in timing methods is verified by design and
characterization but not subject to production test. In single
ended mode, the DQS (and RDQS) signals are internally
disabled and don’t care.
relative to the rising or falling edges of DQS crossing at VREF
.
TABLE 25
DC & AC Logic Input Levels for DDR2-667 and DDR2-800
Symbol
Parameter
DDR2-667, DDR2-800
Units
Min.
Max.
VIH(dc)
VIL(dc)
VIH(ac)
VIL(ac)
DC input logic high
DC input low
V
REF + 0.125
V
V
DDQ + 0.3
REF – 0.125
V
V
V
V
–0.3
AC input logic high
AC input low
V
REF + 0.200
—
—
VREF – 0.200
TABLE 26
DC & AC Logic Input Levels for DDR2-533 and DDR2-400
Symbol
Parameter
DDR2-533, DDR2-400
Units
Min.
Max.
VIH(dc)
VIL(dc)
VIH(ac)
VIL(ac)
DC input logic high
DC input low
V
REF + 0.125
V
V
DDQ + 0.3
REF - 0.125
V
V
V
V
–0.3
AC input logic high
AC input low
V
REF + 0.250
—
—
VREF - 0.250
Rev. 1.12, 2007-05
30
10062006-YPTZ-CDR7
QIMONDA [ QIMONDA AG ]
