Internet Data Sheet
HY[B/I]18T512[40/80/16]0B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
2.2
512 Mbit DDR2 Addressing
This chapter contents the table for the 512 Mbit DDR2 Addressing.
TABLE 10
512-Mbit DDR2 Addressing
Configuration
128Mb x 41)
64Mb x 81)
32Mb x 161)
Note
Bank Address
BA[1:0]
4
BA[1:0]
4
BA[1:0]
4
Number of Banks
Auto-Precharge
A10 / AP
A[13:0]
A11, A[9:0]
11
A10 / AP
A[13:0]
A[9:0]
10
A10 / AP
A[12:0]
A[9:0]
10
Row Address
Column Address
Number of Column Address Bits
Number of I/Os
2)
3)
4
8
16
Page Size [Bytes]
1024 (1K)
1024 (1K)
2048 (2K)
1) Refered to as ’org’
2) Refered to as ’colbits’
3) PageSize = 2colbits × org/8 [Bytes]
Rev. 1.12, 2007-05
18
10062006-YPTZ-CDR7
QIMONDA [ QIMONDA AG ]
