Internet Data Sheet
HY[B/I]18T512[40/80/16]0B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
FIGURE 1
Chip Configuration for ×4 components, PG-TFBGA-60 (top view)
ꢂ
ꢁ
ꢄ
ꢉ
ꢆ
!
"
#
$
%
&
'
(
*
ꢈ
ꢅ
ꢊ
ꢇ
6$$
633
6331
6$$1
.#
$13
6331
6331
.#
$-
$13
.#
6$$1
6$$1
6$$1
6$$1
$1ꢂ
6331
62%&
$1ꢀ
6331
.#
$1ꢄ
$1ꢁ
633$,
2!3
#!3
!ꢁ
.#
6$$,
633
6$$
#+
#+
#3
!ꢀ
!ꢉ
!ꢊ
#+%
"!ꢀ
7%
/$4
6$$
633
.#
633
6$$
"!ꢂ
!ꢂꢀꢃ!0 !ꢂ
!ꢄ
!ꢅ
!ꢆ
!ꢇ
.#
!ꢈ
+
,
!ꢂꢂ
!ꢂꢁ
.# .#ꢋ!ꢂꢄ
-004ꢀꢀꢁꢀ
Notes
1. VDDL and VSSDL are power and ground for the DLL. VDDL is
2. Ball position L8 is A13 for 512-Mbit and is Not Connected
on 256-Mbit
connected to VDD on the device. VDD, VDDQ, VSSDL, VSS
,
and VSSQ are isolated on the device.
Rev. 1.12, 2007-05
15
10062006-YPTZ-CDR7