Internet Data Sheet
HY[B/I]18T512[40/80/16]0B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
FIGURE 1
Chip Configuration for ×4 components, PG-TFBGA-60 (top view)
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Notes
1. VDDL and VSSDL are power and ground for the DLL. VDDL is
2. Ball position L8 is A13 for 512-Mbit and is Not Connected
on 256-Mbit
connected to VDD on the device. VDD, VDDQ, VSSDL, VSS
,
and VSSQ are isolated on the device.
Rev. 1.12, 2007-05
15
10062006-YPTZ-CDR7
QIMONDA [ QIMONDA AG ]
