Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
4
Truth Tables
This chapter describes the truth tables.
TABLE 16
Command Truth Table
Function
CKE
CS RAS CAS WE BA0 A[12:11] A10 A[9:0]
Note1)2)3)
BA1
Previous Current
Cycle
Cycle
4)5)6)
4)
(Extended) Mode Register Set H
H
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
H
L
H
L
L
L
L
BA OP Code
Auto-Refresh
H
H
L
L
L
H
H
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
4)7)
Self-Refresh Entry
Self-Refresh Exit
L
L
4)7)8)
H
X
H
L
X
H
H
H
H
L
4)5)
Single Bank Precharge
Precharge all Banks
Bank Activate
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
L
BA
X
X
X
L
X
X
4)5)
L
L
H
4)5)
L
H
L
BA Row Address
4)5)9)
4)5)9)
4)5)9)
4)5)9)
4)
Write
H
H
H
H
H
X
X
H
X
H
BA Column
BA Column
BA Column
BA Column
L
Column
Column
Column
Column
X
Write with Auto-Precharge
Read
L
L
H
L
L
H
H
H
X
X
H
X
H
Read with Auto-Precharge
No Operation
L
H
X
X
X
H
X
X
H
X
H
X
X
X
X
X
X
4)
Device Deselect
Power Down Entry
X
4)10)
X
4)10)
Power Down Exit
L
H
X
X
X
X
1) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
2) “X” means H or L (but a defined logic level)”.
3) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS and CKE at the rising edge of the clock.
5) Bank addresses BA[1:0] determine which bank is to be operated upon. For (E)MRS BA[1:0] selects an (Extended) Mode Register.
6) All banks must be in a precharged idle state, CKE must be high at least for tXP and all read/write bursts must be finished before the
(Extended) Mode Register set Command is issued.
7)
VREF must be maintained during Self Refresh operation.
8) Self Refresh Exit is asynchronous.
9) Burst reads or writes at BL = 4 cannot be terminated. See Chapter 3.5 for details.
10)The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh
requirements.
Rev. 1.50, 2007-12
25
03062006-7M17-PXBC
QIMONDA [ QIMONDA AG ]
