Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
5.2
DC Characteristics
TABLE 21
Recommended DC Operating Conditions (SSTL_18)
Symbol
Parameter
Rating
Min.
Unit
Note
Typ.
Max.
1)
VDD
Supply Voltage
1.7
1.8
1.9
V
V
V
V
V
1)
VDDDL
VDDQ
VREF
VTT
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
1.7
1.8
1.9
1)
1.7
1.8
1.9
2)3)
4)
0.49 × VDDQ
0.5 × VDDQ
VREF
0.51 × VDDQ
V
REF – 0.04
VREF + 0.04
1)
VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together.
2) The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to
be about 0.5 × VDDQ of the transmitting device and VREF is expected to track variations in VDDQ
3) Peak to peak ac noise on VREF may not exceed ± 2% VREF (dc)
.
4)
V
TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in die dc level of VREF
.
TABLE 22
ODT DC Electrical Characteristics
Parameter / Condition
Symbol Min. Nom. Max. Unit Note
1)
Termination resistor impedance value for EMRS(1)[A6,A2] = [0,1]; 75 Ohm Rtt1(eff) 60
Termination resistor impedance value for EMRS(1)[A6,A2] =[1,0]; 150 Ohm Rtt2(eff) 120
75
150
50
90
Ω
Ω
Ω
%
1)
180
60
1)2)
3)
Termination resistor impedance value for EMRS(1)(A6,A2)=[1,1]; 50 Ohm
Deviation of VM with respect to VDDQ / 2
Rtt3(eff) 40
delta VM –6.00
—
+6.00
1) Measurement Definition for Rtt(eff): Apply VIH(ac) and VIL(ac) to test pin separately, then measure current I(VIHac) and I(VILac) respectively.
Rtt(eff) = (VIH(ac) – VIL(ac)) /(I(VIHac) – I(VILac)).
2) Optional for DDR2-400, DDR2-533 and DDR2-667, mandatory for DDR2-800.
3) Measurement Definition for VM: Turn ODT on and measure voltage (VM) at test pin (midpoint) with no load: delta VM = ((2 x VM / VDDQ) –
1) x 100%
TABLE 23
Input and Output Leakage Currents
Symbol
Parameter / Condition
Min.
Max.
Unit
Note
1)
IIL
Input Leakage Current; any input 0 V < VIN < VDD
Output Leakage Current; 0 V < VOUT < VDDQ
–2
–5
+2
+5
μA
μA
2)
IOL
1) All other pins not under test = 0 V
2) DQ’s, LDQS, LDQS, UDQS, UDQS, DQS, DQS, RDQS, RDQS are disabled and ODT is turned off
Rev. 1.50, 2007-12
28
03062006-7M17-PXBC
QIMONDA [ QIMONDA AG ]
