Internet Data Sheet
HY[B/I]18T1G[40/80/16]0C2[C/F]
1-Gbit Double-Data-Rate-Two SDRAM
Parameter
Symbol
DDR2–1066
Min.
Unit
Note1)2)3)4)5)
6)7)
Max.
25)
DQ/DQS output hold time from DQS
DQ hold skew factor
tQH
t
HP – tQHS
—
ps
ps
μs
μs
ns
26)
tQHS
tREFI
—
250
7.8
3.9
—
27)28)
27)29)
30)
Average periodic refresh Interval
—
—
Auto-Refresh to Active/Auto-Refresh command tRFC
127.5
period
31)32)
31)33)
34)
Read preamble
Read postamble
tRPRE
tRPST
0.9
0.4
7.5
1.1
0.6
—
tCK.AVG
tCK.AVG
ns
Active to active command period for 1KB page tRRD
size products
34)
34)
Active to active command period for 2KB page tRRD
size products
10
—
ns
Internal Read to Precharge command delay
Write preamble
tRTP
7.5
—
—
0.6
—
—
—
—
ns
tWPRE
tWPST
tWR
0.35
0.4
tCK.AVG
tCK.AVG
ns
Write postamble
34)
Write recovery time
15
34)35)
Internal write to read command delay
Exit power down to read command
tWTR
tXARD
7.5
ns
3
nCK
nCK
Exit active power-down mode to read command tXARDS
10 – AL
(slow exit, lower power)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
tXP
3
—
nCK
34)
Exit self-refresh to a non-read command
Exit self-refresh to read command
tXSNR
tXSRD
t
RFC +10
—
—
ns
200
nCK
nCK
Write command to DQS associated clock edges WL
RL – 1
TABLE 39
DRAM Component Timing Parameter by Speed Grade - DDR2–800 and DDR2–667
Parameter
Symbol DDR2–800
DDR2–667
Unit
Note1)2)3
)4)5)6)7)
Min.
Max.
Min.
Max.
8)
DQ output access time from CK / CK tAC
–400
2
+400
—
–450
2
+450
—
ps
CAS to CAS command delay
Average clock high pulse width
Average clock period
tCCD
tCH.AVG
tCK.AVG
nCK
tCK.AVG
ps
9)10)
11)
0.48
2500
3
0.52
8000
—
0.48
3000
3
0.52
8000
—
CKE minimum pulse width ( high and tCKE
nCK
low pulse width)
9)10)
Average clock low pulse width
tCL.AVG
tDAL
0.48
0.52
—
0.48
0.52
—
tCK.AVG
12)13)
Auto-Precharge write recovery +
precharge time
WR + tnRP
WR + tnRP
nCK
Rev. 1.02, 2008-01
44
09262007-3YK7-BKKG
QIMONDA [ QIMONDA AG ]
