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HYB18T1G[40/80/16]0AF(L)–[3S/3.7/5]
1-Gbit DDR2 SDRAM
Functional Description
3
Functional Description
The functional description of Double-Data-Rate-Two-SDRAMs is described in full detail in this chapter.
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Table 8
Field
BA2
Mode Register Definition (BA[2:0] = 000B)
Bits Type1)
Description
reg. addr. Bank Address [2]
Note:BA2 not available on 256 Mbit and 512 Mbit components
0B BA2, Bank Address
Bank Address [1]
16
BA1
BA0
A13
15
14
13
0B
BA1, Bank Address
Bank Address [0]
0B
BA0, Bank Address
Address Bus[13]
Note:A13 is not available for 256 Mbit and x16 512 Mbit configuration
0B A13, Address bit 13
Active Power-Down Mode Select
PD
12
w
0B
PD, Fast exit
1B
PD, Slow exit
WR
[11:9] w
Write Recovery2)
Note:All other bit combinations are illegal.
001B WR, 2
010B WR, 3
011B WR, 4
100B WR, 5
101B WR, 6
DLL
TM
CL
8
w
w
w
DLL Reset
0B
1B
DLL, No
DLL, Yes
7
Test Mode
0B
1B
TM, Normal Mode
TM, Vendor specific test mode
[6:4]
CAS Latency
Note:All other bit combinations are illegal.
011B CL, 3
100B CL, 4
101B CL, 5
110B CL, 6
Internet Data Sheet
15
Rev. 1.31, 2007-01
03292006-1X3H-6X8S
QIMONDA [ QIMONDA AG ]
