HYB18T1G[40/80/16]0AF(L)–[3S/3.7/5]
1-Gbit DDR2 SDRAM
Pin Configuration
2.2
1-Gbit DDR2 Addressing
Table 7
1-Gbit DDR2 Addressing
Configuration
Bank Address
Number of Banks
Auto-Precharge
Row Address
256M x 4
BA[2:0]
8
128M x 8
BA[2:0]
8
64M x 16
BA[2:0]
8
Note
A10 / AP
A[13:0]
A11, A[9:0]
11
A10 / AP
A[13:0]
A[9:0]
10
A10 / AP
A[12:0]
A[9:0]
10
Column Address
1)
Number of Column
Address Bits
2)
3)
Number of I/Os
4
8
16
Page Size [Bytes]
1024 (1K)
1024 (1K)
2048 (2K)
1) Refered to as ’colbits’
2) Refered to as ’org’
3) PageSize = 2colbits × org/8 [Bytes]
Internet Data Sheet
14
Rev. 1.31, 2007-01
03292006-1X3H-6X8S