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HYB18T1G[40/80/16]0AF(L)–[3S/3.7/5]
1-Gbit DDR2 SDRAM
Pin Configuration
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Figure 3
Notes
Pin Configuration for ×16 components, P-TFBGA-92 (top view)
2. LDM is the data mask signal for DQ[7:0], UDM is the
data mask signal for DQ[15:8]
3. VDDL and VDDSL are power and ground for the DLL.
They are connected on the device to VDD and VSS.
1. UDQS/UDQS is data strobe for DQ[15:8],
LDQS/LDQS is data strobe for DQ[7:0]
Internet Data Sheet
13
Rev. 1.31, 2007-01
03292006-1X3H-6X8S
QIMONDA [ QIMONDA AG ]
