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HYB18T1G[40/80/16]0AF(L)–[3S/3.7/5]
1-Gbit DDR2 SDRAM
Pin Configuration
2.1
TFBGA Ball Out Diagrams
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Figure 1
Pin Configuration for ×4 components, PG-TFBGA-68 (top view)
Note:VDDL and VSSDL are power and ground for the DLL. VDDL is connected to VDD on the device. VDD, VDDQ, VSSDL
,
VSS, and VSSQ are isolated on the device.
Internet Data Sheet
11
Rev. 1.31, 2007-01
03292006-1X3H-6X8S
QIMONDA [ QIMONDA AG ]
