Internet Data Sheet
HY[B/E]18M256[16/32]0CF
256-Mbit DDR Mobile-RAM
2.1.2
Extended Mode Register
The Extended Mode Register controls additional low power features of the device. These include the Partial Array Self Refresh
(PASR), the Temperature Compensated Self Refresh (TCSR) and the drive strength selection for the DQs. The Extended
Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 1) and will retain the stored
information until it is programmed again or the device loses power.
The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before
initiating any subsequent operation. Violating either of these requirements result in unspecified operation. Address bits A0 -
A2 specify the Partial Array Self Refresh (PASR) and bits A5 - A6 the Drive Strength, while bits A7 - Amax shall be written
to zero. Bits A3 and A4 are “don’t care” (see below).
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
Mode Register Definition (BA[1:0] = 00B)
%$ꢈ
ꢈ
%$ꢃ
ꢃ
$PD[ꢋꢋꢌꢋꢋ$ꢅ
$ꢉ
$ꢂ
$ꢄ
$ꢁ
$ꢀ
$ꢈ
$ꢃ
ꢃ
ꢃ
'6
ꢍ7&65ꢎ
3$65
ꢃ
ꢃ
ꢃ
ꢃ
03%/ꢃꢈꢁꢃ
Field Bits
DS [6:5]
Type Description
w
Selectable Drive Strength
00B DS Full Drive Strength
01B DS Half Drive Strength
10B DS Quarter Drive Strength
11B DS 1/8 Drive Strength
TCSR [4:3]
PASR [2:0]
w
w
Temperature Compensated Self Refresh
XXB TCSR Superseded by on-chip temperature sensor (see text)
Partial Array Self Refresh
000B PASR all banks
001B PASR half array (BA1 = 0)
010B PASR quarter array (BA1 = BA0 = 0)
Note: All other bit combinations are RESERVED.
Reserved address bits
A
[Amax:7]
w
Note: Amax = A12 for x16, A11 for x32
Rev.1.44, 2007-07
10
06262007-JK8G-48BV
QIMONDA [ QIMONDA AG ]
