Internet Data Sheet
HY[B/E]18M256[16/32]0CF
256-Mbit DDR Mobile-RAM
2.1
Register Definition
Mode Register
2.1.1
The Mode Register is used to define the specific mode of operation of the DDR Mobile-RAM. This definition includes the
selection of a burst length (bits A0-A2), a burst type (bit A3) and a CAS latency (bits A4-A6). The Mode Register is programmed
via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is
programmed again or the device loses power.
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any
subsequent operation. Violating either of these requirements results in unspecified operation.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
Full page bursts wrap within the page if the boundary is reached. Please note that full page bursts do not self-terminate; this
implies that full-page read or write bursts with Auto Precharge are not legal commands. Full page burst has to start from an
even column address.
Mode Register Definition (BA[1:0] = 00B)
%$ꢈ %$ꢃ
$PD[ꢋꢋꢋ±ꢋꢋꢋ$ꢅ
$ꢉ
$ꢂ
&/
$ꢄ
$ꢁ
%7
$ꢀ
$ꢈ
%/
$ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
03%/ꢃꢈꢀꢃ
Field Bits
Type Description
CL
[6:4]
w
CAS Latency
010B CL 2
011B CL 3
Note: All other bit combinations are RESERVED.
BT
BL
3
w
w
Burst Type
0B
1B
BT Sequential
BT Interleaved
[2:0]
Burst Length
001B BL 2
010B BL 4
011B BL 8
100B BL 16
111B BL Full page (Sequential burst type only)
Note: All other bit combinations are RESERVED.
Reserved address bits
A
[Amax:7]
w
Note: Amax = A12 for x16, A11 for x32
Rev.1.44, 2007-07
06262007-JK8G-48BV
9
QIMONDA [ QIMONDA AG ]
