Advance Internet Data Sheet
HY[B/E]18M1G[16/32]0DF–[6/7.5]
1Gbit DDR Mobile-RAM
Field Bits
Type Description
BL
[2:0]
w
Burst Length
001B BL 2
010B BL 4
011B BL 8
100B BL 16
Note: All other bit combinations are RESERVED.
Reserved address bits
A
[12:7]
w
Note: Amax = A13 for x16, A12 for x32
2.1.2
Extended Mode Register
The Extended Mode Register controls additional low power
features of the device. These include the Partial Array Self
Refresh (PASR), the Temperature Compensated Self
Refresh (TCSR) and the drive strength selection for the DQs.
The Extended Mode Register is programmed via the MODE
REGISTER SET command (with BA0 = 0 and BA1 = 1) and
will retain the stored information until it is programmed again
or the device loses power.
The Extended Mode Register must be loaded when all banks
are idle, and the controller must wait the specified time before
initiating any subsequent operation. Violating either of these
requirements result in unspecified operation. Address bits
A0 - A2 specify the Partial Array Self Refresh (PASR) and
bits A5 - A7 the Drive Strength, while bits A8 - Amax shall be
written to zero. Bits A3 and A4 are “don’t care” (see below).
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
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TABLE 6
Extended Mode Register Definition (BA[1:0] = 10B)
Field Bits
DS [7:5]
Type Description
w
Selectable Drive Strength
000B DS Full (25 Ω typ.)
x01B DS Half (50 Ω typ; default)
010B DS Quarter (100 Ω typ.)
011B DS 1/8 (200 Ω typ.)
100B DS 35 Ω typ.
110B DS 65 Ω typ.
111B DS 80 Ω typ.
TCSR [4:3]
w
Temperature Compensated Self Refresh
XXB TCSR Superseded by on-chip temperature sensor (see text)
Rev. 0.81, 2008-04
8
02252008-RRTW-LCC3
QIMONDA [ QIMONDA AG ]
