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HYB18M1G320DF-7.5 参数 Datasheet PDF下载

HYB18M1G320DF-7.5图片预览
型号: HYB18M1G320DF-7.5
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 8MX16, 6ns, CMOS, PBGA90, 9 X 12.50 MM, 1 MM HEIGHT, GREEN, PLASTIC, VFBGA-90]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 23 页 / 1042 K
品牌: QIMONDA [ QIMONDA AG ]
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Advance Internet Data Sheet  
HY[B/E]18M1G[16/32]0DF–[6/7.5]  
1Gbit DDR Mobile-RAM  
TABLE 3  
Ordering Information  
Type1)  
Description  
Package  
Commercial Temperature Range  
HYB18M1G160DF–[6/7.5]  
HYB18M1G320DF–[6/7.5]  
166/133 MHz 4 banks ×16 Mbit ×16 Low Power DDR SDRAM  
166/133 MHz 4 Banks × 8 Mbit × 32 Low Power DDR SDRAM  
60–ball BGA  
90–ball BGA  
Extended Temperature Range  
HYE18M1G160DF–[6/7.5]  
HYE18M1G320DF–[6/7.5]  
166/133 MHz 4 banks ×16 Mbit ×16 Low Power DDR SDRAM  
166/133 MHz 4 Banks × 8 Mbit × 32 Low Power DDR SDRAM  
60–ball BGA  
90–ball BGA  
1) HY[B/E]: Designator for memory products (HYB: Commercial temperature range, HYE: Extended temperature range)  
18M: 1.8 V DDR Mobile-RAM  
1G: 1Gbit density  
16/32: 16 or 32 bit interface width  
0: Product variant  
D: die revision  
F: green BGA product  
-6/-7.5: speed grades (min. clock cycle time)  
1.2  
Description  
Qimonda 1-Gbit DDR Mobile-RAM is a high-speed CMOS,  
dynamic random-access memory containing 1073741824  
bits. It is internally configured as a quad-bank DRAM.  
DDR Mobile-RAM is especially designed for mobile  
applications. It operates from a 1.8 V power supply. Power  
consumption in self refresh mode is drastically reduced by an  
On-Chip Temperature Sensor (OCTS); it can further be  
reduced by using the programmable Partial Array Self  
Refresh (PASR). A conventional data-retaining Power-Down  
(PD) mode is available as well as a non-data-retaining Deep  
Power-Down (DPD) mode. For further power-savings the  
clock may be stopped during idle periods.  
DDR Mobile-RAM uses a double-data-rate architecture to  
achieve high-speed operation. The double-data-rate  
architecture is essentially a 2n pre fetch architecture, with an  
interface designed to transfer two or four data words per clock  
cycle at the I/O pins. A single READ or WRITE access for the  
DRAM consists of a single 2n-bit wide, one clock cycle data  
transfer at the internal DRAM core and two corresponding n-  
bit wide, one-half clock cycle data transfers at the I/O pins.  
The 1-Gbit DRAM is available in commercial (0 °C to +70 °C)  
and extended (-25 °C to +85 °C) temperature ranges.  
Rev. 0.81, 2008-04  
4
02252008-RRTW-LCC3