HY[B/E]18L256160B[C/F]X-7.5
256-Mbit Mobile-RAM
Overview
1.3
Description
The HY[B/E]18L256160B[C/F]X is a high-speed CMOS, dynamic random-access memory containing
268,435,456 bits. It is internally configured as a quad-bank DRAM.
The HY[B/E]18L256160B[C/F]X achieves high speed data transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output data to the system clock. Read and write accesses are
burst-oriented; accesses start at a selected location and continue for a programmed number of locations (1, 2, 4,
8 or full page) in a programmed sequence.
The device operation is fully synchronous: all inputs are registered at the positive edge of CLK.
The HY[B/E]18L256160B[C/F]X is especially designed for mobile applications. It operates from a 1.8V power
supply. Power consumption in self refresh mode is drastically reduced by an On-Chip Temperature Sensor
(OCTS); it can further be reduced by using the programmable Partial Array Self Refresh (PASR).
A conventional data-retaining Power-Down (PD) mode is available as well as a non-data-retaining Deep Power-
Down (DPD) mode.
The HY[B/E]18L256160B[C/F]X is housed in a 54-ball P-VFBGA package. It is available in Commercial (0 °C to
70 °C) and Extended (-25 °C to 85 °C) temperature range.
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Figure 2
Functional Block Diagram
Data Sheet
5
Rev. 1.11, 2007-01
07142005-CR47-RB2E
QIMONDA [ QIMONDA AG ]
