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HYB18L256160BCX-7.5 参数 Datasheet PDF下载

HYB18L256160BCX-7.5图片预览
型号: HYB18L256160BCX-7.5
PDF下载: 下载PDF文件 查看货源
内容描述: DRAM的移动应用256兆移动-RAM [DRAMs for Mobile Applications 256-Mbit Mobile-RAM]
分类和应用: 存储内存集成电路动态存储器时钟
文件页数/大小: 48 页 / 1590 K
品牌: QIMONDA [ QIMONDA AG ]
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HY[B/E]18L256160B[C/F]X-7.5  
256-Mbit Mobile-RAM  
Functional Description  
1. At first, device core power (VDD) and device IO power (VDDQ) must be brought up simultaneously. Typically  
VDD and VDDQ are driven from a single power converter output.  
Assert and hold CKE and DQM to a HIGH level.  
2. After VDD and VDDQ are stable and CKE is HIGH, apply stable clocks.  
3. Wait for 200µs while issuing NOP or DESELECT commands.  
4. Issue a PRECHARGE ALL command, followed by NOP or DESELECT commands for at least tRP period.  
5. Issue two AUTO REFRESH commands, each followed by NOP or DESELECT commands for at least tRC  
period.  
6. Issue two MODE REGISTER SET commands for programming the Mode Register and Extended Mode  
Register, each followed by NOP or DESELECT commands for at least tMRD period; the order in which both  
registers are programmed is not important. Programming of the Extended Mode Register may be omitted when  
default values (half drive strength, 4 bank refresh) will be used.  
Following these steps, the Mobile-RAM is ready for normal operation.  
2.2  
Register Definition  
Mode Register  
2.2.1  
The Mode Register is used to define the specific mode of operation of the Mobile-RAM. This definition includes  
the selection of a burst length (bits A0-A2), a burst type (bit A3), a CAS latency (bits A4-A6), and a write burst  
mode (bit A9). The Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and  
BA1 = 0) and will retain the stored information until it is programmed again or the device loses power.  
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before  
initiating any subsequent operation. Violating either of these requirements results in unspecified operation.  
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.  
MR  
Mode Register Definition  
(BA[1:0] = 00B)  
BA1  
BA0  
A12  
A11  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
0
0
0
0
0
WB  
0
0
CL  
BT  
BL  
Field Bits Type Description  
WB  
9
w
Write Burst Mode  
0
1
Burst Write  
Single Write  
CL  
[6:4]  
w
CAS Latency  
010 2  
011 3  
Note:All other bit combinations are RESERVED.  
BT  
3
w
Burst Type  
0
1
Sequential  
Interleaved  
Data Sheet  
8
Rev. 1.11, 2007-01  
07142005-CR47-RB2E