512-Mbit GDDR3 Graphics RAM
HYB18H512321AF
HYB18H512321AF–12/14/16/20
HYB18H512321AFL14/16/20
1
Overview
1.1
Features
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2.0 V VDDQ IO voltage HYB18H512321AF–12/14/16/20
2.0 V VDD core voltage HYB18H512321AF–12/14/16/20
1.8 V VDDQ IO voltage HYB18H512321AFL14/16/20
1.8 V VDD core voltage HYB18H512321AFL14/16/20
Organization: 2048K × 32 × 8 banks
4096 rows and 512 columns (128 burst start locations) per bank
Differential clock inputs (CLK and CLK)
CAS latencies of 7, 8, 9, 10, 11
Write latencies of 3, 4
Burst sequence with length of 4, 8.
4n prefetch
Short RAS to CAS timing for Writes
t
t
RAS Lockout support
WR programmable for Writes with Auto-Precharge
Data mask for write commands
Single ended READ strobe (RDQS) per byte. RDQS edge-aligned with READ data
Single ended WRITE strobe (WDQS) per byte. WDQS center-aligned with WRITE data
DLL aligns RDQS and DQ transitions with Clock
Programmable IO interface including on chip termination (ODT)
Autoprecharge option with concurrent autoprecharge support
8k Refresh (32ms)
Autorefresh and Self Refresh
PG-TFBGA 136 package (11mm × 14mm)
Calibrated output drive. Active termination support
RoHS Compliant Product1)
1)RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and
electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council
of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated
biphenyls and polybrominated biphenyl ethers.
Data Sheet
9
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
