HYB18H512321AF
512-Mbit GDDR3
Pin Configuration
Table 2
Ball
Ball Description
Type Detailed Function
ZQ
-
ODT Impedance Reference: The ZQ ball is used to control the ODT impedance.
RES
Input Reset pin: The RES pin is a VDDQ CMOS input. RES is not internally terminated. When
RES is at LOW state the chip goes into full reset. The chip stays in full reset until RES goes
to HIGH state. The Low to High transition of the RES signal is used to latch the CKE value
to set the value of the termination resistors of the address and command inputs. After
exiting the full reset a complete initialization is required since the full reset set the internal
settings to default.
MF
Input Mirror function pin: The MF pin is a VDDQ CMOS input. This pin must be hardwired on
board either to a power or to a ground plane. With MF set to HIGH, the command and
address pins are reassigned in order to allow for an easier routing on board for a back to
back memory arrangement.
SEN
VREF
Input Enables Boundary Scan Functionality. If Boundary Scan is not used PIN should be
constantly connected to GND.
Supply Voltage Reference: VREF is the reference voltage input.
VDD, VSS,
VDDA, VSSA
Supply Power Supply: Power and Ground for the internal logic. VDD and VDDA must be provided
by the same power rail. Shorted in the package.
VDDQ, VSSQ Supply I/O Power Supply: Isolated Power and Ground for the output buffers to provide improved
noise immunity.
NC, RFU
-
Please do not connect No Connect and Reserved for Future Use balls.
2.2
Mirror Function
The GDDR3 Graphics RAM provides a ball mirroring feature that is enabled by applying a logic HIGH on ball MF.
This function allows for efficient routing in a clam shell configuration.
Depending of the logic state applied on MF, the command and address signals will be assigned to different balls.
The default ball configuration (see Figure 1) correponds to MF = LOW.
The DC level (HIGH or LOW) must be applied on the MF pin at power up and is not allowed to change after that.
Table 3 shows the ball assignment as a function of the logic state applied on MF.
Table 3
Ball Assignment with Mirror
MF Logic State
Signal
LOW
H3
F4
H9
F9
HIGH
H10
F9
H4
F4
RAS
CAS
WE
CS
CKE
A0
H4
K4
H9
K9
H2
K3
M4
K9
H11
K10
M9
K4
A1
A2
A3
A4
H11
K10
H2
K3
A5
A6
Data Sheet
13
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
