HYB18H512321AF
512-Mbit GDDR3
Pin Configuration
2.1
Ball Definition and Description
Table 2
Ball
Ball Description
Type Detailed Function
CLK, CLK
Input Clock: CLK and CLK are differential clock inputs. Address and command inputs are
latched on the positive edge of CLK. Graphics SDRAM outputs (RDQS, DQs) are
referenced to CLK. CLK and CLK are not internally terminated.
CKE
Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock and
input buffers. Taking CKE LOW provides Power Down. If all banks are precharged, this
mode is called Precharge Power Down and Self Refresh mode is entered if a Auto Refresh
command is issued. If at least one bank is open, Active Power Down mode is entered and
no Self Refresh is allowed. All input receivers except CLK, CLK and CKE are disabled
during Power Down. In Self Refresh mode the clock receivers are disabled too. Self
Refresh Exit is performed by setting CKE asynchronously HIGH. Exit of Power Down
without Self Refresh is accomplished by setting CKE HIGH with a positive edge of CLK.
The value of CKE is latched asynchronously by Reset during Power On to determine the
value of the termination resistor of the address and command inputs.
CKE is not allowed to go LOW during a RD, a WR or a snoop burst.
CS
Input Chip Select: CS enables the command decoder when low and disables it when high.
When the command decoder is disabled, new commands with the exeption of DTERDIS
are ignored, but internal operations continue. CS is one of the four command balls.
RAS, CAS, Input Command Inputs: Sampled at the positive edge of CLK, CAS, RAS, and WE define
WE
(together with CS) the command to be executed.
DQ<0:31>
I/O
Data Input/Output: The DQ signals form the 32 bit data bus. During READs the balls are
outputs and during WRITEs they are inputs. Data is transferred at both edges of RDQS.
DM<0:3>
Input Input Data Mask: The DM signals are input mask signals for WRITE data. Data is masked
when DM is sampled HIGH with the WRITE data. DM is sampled on both edges of WDQS.
DM0 is for DQ<0:7>, DM1 is for DQ<8:15>, DM2 is for DQ<16:23> and DM3 is for
DQ<24:31>. Although DM balls are input-only, their loading is designed to match the DQ
and WDQS balls.
RDQS<0:3> Output Read Data Strobes: RDQSx are unidirectional strobe signals. During READs the RDQSx
are transmitted by the Graphics SDRAM and edge-aligned with data. RDQS have
preamble and postamble requirements. RDQS0 is for DQ<0:7>, RDQS1 for DQ<8:15>,
RDQS2 for DQ<16:23> and RDQS3 for DQ<24:31>.
WDQS<0:3> Input Write Data Strobes: WDQS are unidirectional strobe signals. During WRITEs the WDQS
are generated by the controller and center aligned with data. WDQS have preamble and
postamble requirements. WDQS0 is for DQ<0:7>, WDQS1 for DQ<8:15>, WDQS2 for
DQ<16:23> and WDQS3 for DQ<24:31>.
BA<0:2>
Input Bank Address Inputs: BA select to which internal bank an ACTIVATE, READ, WRITE or
PRECHARGE command is being applied. BA are also used to distinguish between the
MODE REGISTER SET and EXTENDED MODE REGISTER SET commands.
A<0:11>
Input Address Inputs: During ACTIVATE, A0-A11 defines the row address. For READ/WRITE,
A2-A7 and A9 defines the column address, and A8 defines the auto precharge bit. If A8 is
HIGH, the accessed bank is precharged after execution of the column access. If A8 is
LOW, AUTO PRECHARGE is disabled and the bank remains active. Sampled with
PRECHARGE, A8 determines whether one bank is precharged (selected by BA<0:2>, A8
LOW) or all 8 banks are precharged (A8 HIGH). During (EXTENDED) MODE REGISTER
SET the address inputs define the register settings. A<0:11> are sampled with the positive
edge of CLK.
Data Sheet
12
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
