HYB18H512321AF
512-Mbit GDDR3
Electrical Characteristics
5.3
DC & AC Logic Input Levels
5.4
Table 28
Parameter
Differential Clock DC and AC Levels
DC & AC Logic Input Levels ( 0 °C ≤ Tc ≤ 85 °C)
Symbol
Limit Values
min.
Unit Note
s
max.
—
1)
Input logic high voltage, DC
Input logic low voltage, DC
Input logic high voltage, AC
Input logic low voltage, AC
Input logic high, DC, RESET pin
Input logic low, DC, RESET pin
Input Logic High, DC, MF pin
Input Logic Low,DC, MF pin
VIH(DC)
VIL(DC)
VIH(AC)
VIL(AC)
V
—
V
—
REF + 0.15
V
1)
VREF -0.15
V
V
V
V
V
V
V
2) 3)
REF + 0.25
—
,
,
2) 3)
V
V
REF - 0.25
DDQ + 0.3
V
V
V
V
IHR(DC)
ILR(DC)
IHMF(DC) VDD
ILMF(DC) –0.3
0.65.VDDQ
-0.3
0.35.VDDQ
4)
VDD + 0.3
0
1) The DC values define where the input slew rate requirements are imposed, and the input signal must not
violate these levels in order to maintain a valid level.
2) Input slew rate = 3V/ns. If the input slew rate is less than 3V/ns, input timing may be compromised. All slew
rates are measured between VIL(DC) and VIH(DC).
3) VIH overshoot : VIH(max) = VDDQ+0.5V for a pulse width ≤ 500ps and the pulse width cannot be greater than 1/3
of the cycle rate. VIL undershoot: VIL(min) = 0V for a pulse width ≤ 500ps and the pulse width cannot be greater
than 1/3 of the cycle rate.
4) The MF pin must be hard-wired on board to either VDD or VSS.
Table 29
Differential Clock DC and AC Input conditions ( 0 °C ≤ Tc ≤ 85 °C)
Parameter
Symbol Limit Values
Unit Notes
min.
Clock Input Mid-Point Voltage, CLK and CLK VMP(DC) 0.7 × VDDQ – 0.10
max.
0.7 × VDDQ + 0.10 V
1)
1)
1)
Clock Input Voltage Level, CLK and CLK
VIN(DC)
0.42
V
DDQ + 0.3
V
V
Clock DC Input Differential Voltage, CLK and VID(DC)
0.3
VDDQ
CLK
1)2)
1)3)
Clock AC Input Differential Voltage, CLK and VID(AC)
0.5
V
DDQ + 0.5
V
CLK
AC Differential Crossing Point Input Voltage VIX(AC)
1) All voltages referenced to VSS.
0.7 × VDDQ – 0.15
0.7 × VDDQ + 0.15 V
2) VID is the magnitude of the difference between the input level on CLK and the input level on CLK.
3) The value of VIX is expected to equal 0.7 × VDDQ of the transmitting device and must track variations in the DC
level of the same.
Data Sheet
82
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
