Internet Data Sheet
HYB18H512321BF
512-Mbit GDDR3
Parameter
CAS latency Symbol
Limit Values
–11
Unit Note
-8
–10
–12
–14
Min Max Min. Max. Min. Max. Min. Max. Min. Max.
Column Timing
8)
CAS(a) to CAS(b) Command tCCD
period
2
8
—
—
2
7
—
—
2
6
—
—
2
6
—
—
2
5
—
—
tCK
tCK
tCK
9)
Internal write to Read
Command Delay
tWTR
tRTW
10)
Read to Write command
delay
tRTW(min)= (CL + BL/2 +2 -WL)
Write Cycle Timing Parameters for Data and Data Strobe
Write command to first
tDQSS
WL– WL+ WL– WL+ WL– WL+ WL– WL+ WL– WL+ tCK
WDQS latching transition
0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25
Data-in and Data Mask to
WDQS Setup Time
tDS
0.13
0.13
0.4
—
—
—
0.14
0.14
0.40
—
—
—
0.15
0.15
0.40
—
—
—
0.16
0.16
0.40
—
—
—
0.18
0.18
0.40
—
—
—
ns
ns
tCK
Data-in and Data Mask to
WDQS Hold Time
tDH
Data-in and DM input pulse tDIPW
width (each input)
DQS input low pulse width
DQS input high pulse width tDQSH
DQS Write Preamble Time tWPRE
DQS Write Postamble Time tWPST
Write Recovery Time tWR
Read Cycle Timing Parameters for Data and Data Strobe
tDQSL
0.45
—
0.40
—
—
0.40
0.40
—
—
0.40
0.40
—
—
0.40
0.40
—
—
tCK
tCK
0.45
—
0.40
0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK
0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK
13
—
13
—
13
—
12
—
10
—
tCK
Data Access Time from
Clock
tAC
-0.20 -0.20 -0.21 0.21 -0.22 0.22 -0.22 0.22 –0.25 0.25 ns
Read Preamble
Read Postamble
tRPRE
tRPST
tHZ
0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK
0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK
tACmin tACmax tACmin tACmax tACmin tACmax tACmin tACmax tACmin tACmax ns
Data-out high impedance
time from CLK
Data-out low impedance time tLZ
tACmin tACmax tACmin tACmax tACmin tACmax tACmin tACmax tACmin tACmax ns
from CLK
DQS edge to Clock edge
skew
tDQSCK
-0.20 0.20 -0.21 0.21 -0.22 0.22 -0.22 0.22 –0.25 0.25 ns
11)
DQS edge to output data
edge skew
tDQSQ
—
—
0.110 —
0.110 —
0.120 —
0.120 —
0.130 —
0.130 —
0.140 —
0.140 —
0.160 ns
Data hold skew factor
tQHS
tQH
0.160 ns
ns
Data output hold time from
DQS
tHP–tQHS
Refresh/Power Down Timing
Refresh Period (8192 cycles) tREF
—
32
—
32
—
32
—
32
—
32
ms
Average periodic Auto
Refresh interval
tREFI
3.9
3.9
3.9
3.9
3.9
μs
Rev. 1.3, 2007-12
33
05292007-WAU2-UU95
QIMONDA [ QIMONDA AG ]
