Internet Data Sheet
HYB18H512321BF
512-Mbit GDDR3
4.12
AC Timings for HYB18H512321BF
TABLE 20
Timing Parameters for HYB18H512321BF
Parameter
CAS latency Symbol
Limit Values
–11
Min Max Min. Max. Min. Max. Min. Max. Min. Max.
Unit Note
-8
–10
–12
–14
Clock and Clock Enable
1)
System
frequency
CL=13
CL= 12
CL= 11
CL =10
CL = 9
CL = 8
CL = 7
fCK13
fCK12
fCK11
fCK10
fCK9
fCK8
fCK7
tCH
700 1200
—
—
—
—
—
—
—
—
—
—
—
—
MHz
1)
500 1000 500 1000
—
—
MHz
1)
400 900
350 800
350 700
350 600
350 550
400 900
350 800
350 700
350 600
350 550
400 900
350 800
350 700
350 600
350 550
400 800
350 700
350 650
350 550
350 500
400
350
350
350
350
700
650
600
500
450
MHz
1)2)
MHz
1)2)
MHz
1)2)
MHz
1)2)
MHz
Clock high level width
Clock low-level width
Minimum clock half period
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK
tCL
3)
tHP
0.45
—
0.45
—
0.45
—
0.45
—
0.45
—
tCK
Command and Address Setup and Hold Timing
Address/Command input
setup time
tIS
0.22
0.22
0.7
—
—
—
0.24
0.24
0.7
—
—
—
0.27
0.27
0.7
—
—
—
0.3
0.3
0.7
—
—
—
0.35
0.35
0.7
—
—
—
ns
ns
tCK
Address/Command input
hold time
tIH
Address/Command input
pulse width
tIPW
Mode Register Set Timing
4)5)
Mode Register Set cycle time tMRD
6
—
—
6
—
—
6
—
—
6
—
—
6
—
—
tCK
tCK
Mode Register Set to READ tMRDR
12
12
12
12
12
timing
Row Timing
Row Cycle Time
Row Active Time
tRC
40
25
10
—
—
—
37
23
9
—
—
—
35
22
8
—
—
—
34
21
8
—
—
—
30
18
7
—
—
—
tCK
tCK
tCK
6)
tRAS
ACT(a) to ACT(b) Command tRRD
period
Row Precharge Time
tRP
15
14
—
—
14
13
—
—
13
12
—
—
13
12
—
—
12
11
—
—
tCK
tCK
Row to Column Delay Time tRCDRD
for Reads
7)
Row to Column Delay Time tRCDWR
for Writes
t
RCDWR(Min) = max(tRCDRD(Min) - (WL + 1) × tCK;2×tCK
)
tCK
tCK
Four Active Windows within tFAW
40
—
36 32 32 28
—
—
—
—
Rank
Rev. 1.3, 2007-12
32
05292007-WAU2-UU95
QIMONDA [ QIMONDA AG ]
