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HYB18H256321BF-14 参数 Datasheet PDF下载

HYB18H256321BF-14图片预览
型号: HYB18H256321BF-14
PDF下载: 下载PDF文件 查看货源
内容描述: 256兆GDDR3图形内存GDDR3图形内存 [256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 41 页 / 2032 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYB18H256321BF  
256-Mbit GDDR3  
3.2  
Extended Mode Register Set Command (EMRS1)  
The Extended Mode Register is used to set the output driver  
impedance value, the termination impedance value, the Write  
Recovery time value for Write with Autoprecharge. It is used  
as well to enable/disable the DLL, to issue the Vendor ID and  
to enable/disable the Low Power mode. There is no default  
value for the Extended Mode Register. Therefore it must be  
written after power up to operate the GDDR3 Graphics RAM.  
FIGURE 6  
Extended Mode Register Set Command  
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The Extended Mode Register can be programmed by  
performing a normal Mode Register Set operation and setting  
the BA0 bit to HIGH and BA1 bits to LOW. All other bits of the  
EMR register are reserved and should be set to LOW.  
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The Extended Mode Register must be loaded when all banks  
are idle and no burst are in progress. The controller must wait  
the specified time tMRD before initiating any subsequent  
operation (Figure 9).  
The timing of the EMRS command operation is equivalent to  
the timing of the MRS command operation.  
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Rev. 0.80, 2007-09  
16  
09132007-07EM-7OYI  
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