Internet Data Sheet
HYB18H256321BF
256-Mbit GDDR3
Parameter
CAS latency
Symbol Limit Values
–10
Unit Note
–11
–12
–14
Min. Max. Min. Max. Min. Max. Min. Max.
Data-in and Data Mask to WDQS Setup tDS
Time
0.14
0.14
0.40
—
—
—
0.15
0.15
0.40
—
—
—
0.16
0.16
0.40
—
—
—
0.18
0.18
0.40
—
—
—
ns
ns
tCK
Data-in and Data Mask to WDQS Hold
Time
tDH
Data-in and DM input pulse width (each tDIPW
input)
DQS input low pulse width
DQS input high pulse width
DQS Write Preamble Time
DQS Write Postamble Time
Write Recovery Time
tDQSL
tDQSH
tWPRE
tWPST
tWR
0.40
0.40
—
—
0.40
0.40
—
—
0.40
0.40
—
—
0.40
0.40
—
—
tCK
tCK
0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK
0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK
8)
13
—
13
—
12
—
10
—
tCK
Read Cycle Timing Parameters for Data and Data Strobe
Data Access Time from Clock
Read Preamble
tAC
-0.21 0.21 -0.22 0.22 -0.22 0.22 –0.25 0.25 ns
0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK
0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK
tACmin tACmax tACmin tACmax tACmin tACmax tACmin tACmax ns
tACmin tACmax tACmin tACmax tACmin tACmax tACmin tACmax ns
-0.21 0.21 -0.22 0.22 -0.22 0.22 –0.25 0.25 ns
tRPRE
tRPST
Read Postamble
Data-out high impedance time from CLK tHZ
Data-out low impedance time from CLK tLZ
DQS edge to Clock edge skew
DQS edge to output data edge skew
Data hold skew factor
tDQSCK
11)
tDQSQ
tQHS
tQH
—
—
0.120 —
0.120 —
0.130 —
0.130 —
0.140 —
0.140 —
0.160 ns
0.160 ns
ns
Data output hold time from DQS
Refresh/Power Down Timing
Refresh Period (8192 cycles)
Average periodic Auto Refresh interval
Delay from AREF to next ACT/ AREF
Self Refresh Exit time
t
HP–tQHS
tREF
tREFI
tRFC
tXSC
tXPN
—
32
—
32
—
32
—
32
ms
μs
3.9
52.0
1000
7
3.9
52.0
1000
7
3.9
52.0
1000
7
3.9
52.0
1000
6
—
—
—
—
—
—
—
—
—
—
—
—
ns
tCK
tCK
Power Down Exit time
Other Timing Parameters
RES to CKE setup timing
tATS
10
10
10
—
—
—
—
—
20
20
10
10
10
—
—
—
—
—
20
20
10
10
10
—
—
—
—
—
20
20
10
10
10
—
—
—
—
—
20
20
ns
ns
ns
ns
ns
RES to CKE hold timing
tATH
tKO
tRIDon
tRIDoff
Termination update Keep Out timing
Rev. ID EMRS to DQ on timing
Rev. ID EMRS to DQ off timing
1) DLL on mode ( -10/-11/-12/-14 fCK(Min )= 400 MHz)
2) DLL on mode ( -10/-11/-12/-14 fCK(Min )= 400 MHz)
3)
tHP is the lesser of tCL minimum and tCH minimum actually applied to the device CLK, CLK inputs
4) This value of tMRD applies only to the case where the “DLL reset” bit is not activated
5)
6)
7)
t
t
t
MRD is defined from MRS to any other command then READ
RASmax is 8*tREF
RCDWR(Min) may not drop below 2 × tCK
Rev. 0.80, 2007-09
34
09132007-07EM-7OYI
QIMONDA [ QIMONDA AG ]
